Ceva D.s.p. Ltd.

Technology Innovation Momentum Fund (israel) Limited Partnership

Tel Aviv University

Omri Eisenbach

Tal Ellenbogen

Ori Avayu

Ran Ditcovski

David Dahan

Gil Drori

Erez Bar-Niv

Erez Bar Niv

An array of optical resonators includes at least a first type of optical resonators each having a resonant response to an optical field at a first wavelength, and a second type of optical resonators each having a resonant response to an optical field at a second wavelength, being different from the first wavelength. The resonant responses can be selected to reduce chromatic aberrations, or to shape a profile of a light beam, or to selectively switch a near field beam.

System and method for controlling light by an array of optical resonators

An array of optical resonators comprises at least a first type of optical resonators each having a resonant response to an optical field at a first wavelength, and a second type of optical resonators each having a resonant response to an optical field at a second wavelength, being different from the first wavelength. The resonant responses can be selected to reduce chromatic aberrations, or to shape a profile of a light beam, or to selectively switch a near field beam.

A method and system for transferring data in a multi ordered memory array from a source memory array to a destination memory array, at least one of which is multi-ordered. A reading memory access unit reads data from the source memory array according to a source access template and a writing memory access unit writes the data to the destination memory array according to a destination access template.

Method and apparatus for accessing a multi ordered memory array

A system having at least one breakpoint generating module and a core processor and method for providing mutual breakpoint capabilities to at least one breakpoint generating module and a core processor in a computing device. Each breakpoint generating module is capable of generating a first breakpoint message for allowing operation of the core processor and each breakpoint generating module to be halted. A second breakpoint message allows operation of the core processor to be halted. The second breakpoint message corresponds to the first breakpoint message. In addition, the core processor generates a third breakpoint message for allowing operation of the core processor and each breakpoint generating module to be halted.

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Tel Aviv, Israel

Omri Eisenbach