Velocity Communication, Inc.

Ikanos Communications, Inc.

Omprakash S Sarmaru

Behrooz Rezvani

Avadhani Shridhar

Raminder Singh Bajwa

Firooz Massoudi

Masoud Eskandari

Sridhar Begur

Sam Heidari

T R Ramesh

Tiruvur R Ramesh

Sam Heid Ari

A Fourier transform processor utilizing discrete circuits each of which is configurable for processing a wide range of sample sizes. A single pipeline supports multiplexed bi-directional transformations between for example the time and frequency domains. In an embodiment of the invention the Fourier Transform processor may be implemented as part of a digital signal processor (DSP). In this embodiment the DSP may implement both the discrete Fourier transform (DFT) and inverse discrete Fourier transform (IDFT) across a wide range of sample sizes and X-DSL protocols. Multiple channels, each with varying ones of the X-DSL protocols can be handled in the same session.

Method and apparatus for a DFT/IDFT engine supporting multiple X-DSL protocols

The current invention provides a DSP which accommodates multiple current X-DSL protocols and is further configurable to support future protocols. The DSP is implemented with shared and dedicated hardware components on both the transmit and receive paths. The DSP implements both the discrete Fourier transform (DFT) and inverse discrete Fourier transform (IDFT) portions across a wide range of sample sizes and X-DSL protocols. Multiple channels, each with varying ones of the X-DSL protocols can be handled in the same session. The DSP offers the speed associated with hardware implementation of the transforms and the flexibility of a software only implementation. Traffic flow is regulated in the chip using a packet based schema in which each packet is associated with a specific channel of upstream and downstream data. Header and control information in each packet is used to govern the processing of each packet as it moves along either the transmit path or receive path. The DSP of the current invention may advantageously be utilized in fields other than communications, such as: medical and other imaging, seismic analysis, radar and other military applications, pattern recognition, signal processing etc. The present invention provides a signal processing architecture that supports scalability of CO/DLC/ONU resources, and allows a significantly more flexible hardware response to the evolving X-DSL standards without over committing of hardware resources. As standards evolve hardware may be reconfigured to support the new standards.

Method and apparatus for a X-DSL communication processor

The current invention provides a digital signal processor which supports multiple X-DSL protocols and a multiplicity of channels on a single chip. Each channel is packetized and each packet includes control information for controlling the performance of the components/modules on the transmit and receive path. Further flexibility is derived from an architecture which incorporates discrete and shared modules on the transmit path and the receive path. The transmit path and receive path modules are collectively controlled by control information in selected ones of the packets and operate on each channel's packets at an appropriate rate, and protocol for the channel. A digital signal processor (DSP) is disclosed which incorporates these features. The DSP exhibits a favorable form factor, and flexibility as to protocols and line codes, and numbers of channels supported.

Method and apparatus for synchronizing a packet based modem supporting multiple X-DSL protocols

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Fremont, CA, United States of America

Omprakash S Sarmaru