Applied Materials, Inc.

Rensselaer Polytechnic Institute

Wake Forest University

Industry-University Cooperation Foundation Hanyang University

Omkaram Nalamasu

Victor Pushparaj

Ajay Kumar

Banqiu Wu

Steven Verhaverbeke

Majeed Foad

Dieter Haas

Byung-Sung Kwak

Kaushal Kishore Singh

Nety M Krishna

Kartik Ramaswamy

Mingwei Zhu

Stefan Bangert

Mahalingam Venkatesan

Vivek Agrawal

Nag B Patibandla

Robert Jan Visser

Xianmin Tang

Anantha K Subramani

Muhammad M Rasheed

Rongjun Wang

Pravin K Narwankar

Cheng-Hsiung Matt Tsai

Dinesh Saigal

Praburam Gopal Raja

Linda B McGown

Yuehua Yu

Manoocher Birang

Shahid Rauf

Leonid Dorf

Samer Banna

David Loren Carroll

Pulickel Madhavapanicker Ajayan

Ralf Hofmann

Bhaskar Kumar

Joseph Grover Gordon, Ii

Nirmalya Maity

Ranga Rao Arnepalli

Michael R Snure

Gary E Dickerson

Frank M Torti

Ashutosh Tiwari

Charles Gay

Gaurav Saraf

Mahesh Arcot

Mukhles Sowwan

Bipin Thakur

Suzy V Torti

Yangkook Sun

Nag B Patibandia

Vikas Gujar

Rao Yalamanchili

Srikant Rao

Claire J Carmalt

Sanjayan Sathasivam

Christopher Stuart Blackman

Steven Akman

Byung-sung Leo Kwak

Joseph G Ii Gordon

Seungmin Oh

Wongi Kim

Suzy Torti

Linda Mcgown

The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, printed circuit board (PCB) assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a substrate core (e.g., a core structure) is implanted with dopants to achieve a desired bulk resistivity or conductivity. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like.

Adapting electrical, mechanical, and thermal properties of package substrates

Fabrication of gallium nitride-based light devices with physical vapor deposition (PVD)-formed aluminum nitride buffer layers is described. Process conditions for a PVD AlN buffer layer are also described. Substrate pretreatments for a PVD aluminum nitride buffer layer are also described. In an example, a method of fabricating a buffer layer above a substrate involves pre-treating a surface of a substrate. The method also involves, subsequently, reactive sputtering an aluminum nitride (AlN) layer on the surface of the substrate from an aluminum-containing target housed in a physical vapor deposition (PVD) chamber with a nitrogen-based gas or plasma.

PVD buffer layers for LED fabrication

The present disclosure provides methods and an apparatus for controlling and modifying line width roughness (LWR) of a photoresist layer with enhanced electron spinning control. In one embodiment, an apparatus for controlling a line width roughness of a photoresist layer disposed on a substrate includes a processing chamber having a chamber body having a top wall, side wall and a bottom wall defining an interior processing region, a support pedestal disposed in the interior processing region of the processing chamber, and a plasma generator source disposed in the processing chamber operable to provide predominantly an electron beam source to the interior processing region.

Methods and apparatus for controlling photoresist line width roughness with enhanced electron spin control

Methods of and factories for thin-film battery manufacturing are described. A method includes operations for fabricating a thin-film battery. A factory includes one or more tool sets for fabricating a thin-film battery.

Methods of and factories for thin-film battery manufacturing

Methods for reducing line width roughness and/or critical dimension nonuniformity in a photoresist pattern are provided herein. In some embodiments, a method of reducing line width roughness along a sidewall of a patterned photoresist layer disposed atop a substrate includes: (a) depositing a first layer atop the sidewall of the patterned photoresist layer; (b) etching the first layer and the sidewall after depositing the first layer to reduce the line width roughness of the patterned photoresist layer. In some embodiments, (a)-(b) may be repeated until the line width roughness is substantially smooth.

Methods for reducing line width roughness and/or critical dimension nonuniformity in a patterned photoresist layer

A method for patterning a magnetic thin film on a substrate includes: providing a pattern about the magnetic thin film, with selective regions of the pattern permitting penetration of energized ions of one or more elements. Energized ions are generated with sufficient energy to penetrate selective regions and a portion of the magnetic thin film adjacent the selective regions. The substrate is placed to receive the energized ions. The portions of the magnetic thin film are rendered to exhibit a magnetic property different than selective other portions. A method for patterning a magnetic media with a magnetic thin film on both sides of the media is also disclosed.

Patterning of magnetic thin film using energized ions

Methods for reducing the line width roughness on a photoresist pattern are provided herein. In some embodiments, a method of processing a patterned photoresist layer disposed atop a substrate includes flowing a process gas into a processing volume of a process chamber having the substrate disposed therein; forming a plasma within the process chamber from the process gas, wherein the plasma has a ion energy of about 1 eV to about 10 eV; and etching the patterned photoresist layer with species from the plasma to at least one of smooth a line width roughness of a sidewall of the patterned photoresist layer or remove debris.

Photoresist treatment method by low bombardment plasma

Methods of and hybrid factories for thin-film battery manufacturing are described. A method includes operations for fabricating a thin-film battery. A hybrid factory includes one or more tool sets for fabricating a thin-film battery.

Methods of and hybrid factories for thin-film battery manufacturing

Embodiments of the present invention generally relate to methods and apparatus for forming an energy storage device. More particularly, embodiments described herein relate to methods of forming electric batteries and electrochemical capacitors. In one embodiment a method of forming a high surface area electrode for use in an energy storage device is provided. The method comprises forming an amorphous silicon layer on a current collector having a conductive surface, immersing the amorphous silicon layer in an electrolytic solution to form a series of interconnected pores in the amorphous silicon layer, and forming carbon nanotubes within the series of interconnected pores of the amorphous silicon layer.

Porous amorphous silicon&#x2014;carbon nanotube composite based electrodes for battery applications

Methods for providing a silicon layer on a photomask substrate surface with minimum defeats for fabricating film stack thereon for EUVL applications are provided. In one embodiment, a method for forming a silicon layer on a photomask substrate includes performing an oxidation process to form a silicon oxide layer on a surface of a first substrate wherein the first substrate comprises a crystalline silicon material, performing an ion implantation process to define a cleavage plane in the first substrate, and bonding the silicon oxide layer to a surface of a second substrate, wherein the second substrate is a quartz photomask.

Methods for controlling defects for extreme ultraviolet lithography (EUVL) photomask substrate

Methods and apparatus for performing an atomic layer deposition lithography process are provided in the present disclosure. In one embodiment, a method for forming features on a material layer in a device includes pulsing a first reactant gas mixture to a surface of a substrate disposed in a processing chamber to form a first monolayer of a material layer on the substrate surface, directing an energetic radiation to treat a first region of the first monolayer, and pulsing a second reactant gas mixture to the substrate surface to selectively form a second monolayer on a second region of the first monolayer.

Atomic layer deposition lithography

Embodiments of the invention provide a method of forming a doped gallium arsenide based (GaAs) layer from a solution based precursor. The doped gallium arsenide based (GaAs) layer formed from the solution based precursor may assist solar cell devices to improve light absorption and conversion efficiency. In one embodiment, a method of forming a solar cell device includes forming a first layer with a first type of dopants doped therein over a surface of a substrate, forming a GaAs based layer on the first layer, and forming a second layer with a second type of dopants doped therein on the GaAs based layer.

High efficiency thin film transistor device with gallium arsenide layer

Solar cells are provided with carbon nanotubes (CNTs) which are used: to define a micron/sub-micron geometry of the solar cells; and/or as charge transporters for efficiently removing charge carriers from the absorber layer to reduce the rate of electron-hole recombination in the absorber layer. A solar cell may comprise: a substrate; a multiplicity of areas of metal catalyst on the surface of the substrate; a multiplicity of carbon nanotube bundles formed on the multiplicity of areas of metal catalyst, each bundle including carbon nanotubes aligned roughly perpendicular to the surface of the substrate; and a photoactive solar cell layer formed over the carbon nanotube bundles and exposed surfaces of the substrate, wherein the photoactive solar cell layer is continuous over the carbon nanotube bundles and the exposed surfaces of the substrate. The photoactive solar cell layer may be comprised of amorphous silicon p/i/n thin films; although, concepts of the present invention are also applicable to solar cells with absorber layers of microcrystalline silicon, SiGe, carbon doped microcrystalline silicon, CIS, CIGS, CISSe and various p-type II-VI binary compounds and ternary and quaternary compounds.

Carbon nanotube-based solar cells

The present invention generally relates to electrochromic (EC) devices, such as used in electrochromic windows (ECWs), and their manufacture. The EC devices may comprise a transparent substrate; a first transparent conductive layer; a doped coloration layer, wherein the coloration layer dopants provide structural stability to the arrangement of atoms in the coloration layer; an electrolyte layer; a doped anode layer over said electrolyte layer, wherein the anode layer dopant provides increased electrically conductivity in the doped anode layer; and a second transparent conductive layer. A method of fabricating an electrochromic device may comprise depositing on a substrate, in sequence, a first transparent conductive layer, a doped coloration layer, an electrolyte layer, a doped anode layer, and a second transparent conductive layer, wherein at least one of the doped coloration layer, the electrolyte layer and the doped anode layer is sputter deposited using a combinatorial plasma deposition process.

Materials and device stack for market viable electrochromic devices

Growing community of inventors

San Jose, CA, United States of America

Omkaram Nalamasu