Motorola Corporation

Motorola Mobility LLC

Omid Tahernia

Barry W Herold

Walter L Davis

David F Willard

Paul T Bennett

Frank E Lambrecht

James C Page

Eric Thomas Eaton

Richard Alexander Erhart

Von Alan Mock

Kenneth R Burch

Mario A Rivas

Alan I Spiro

Allan I Spiro

A communication system () dynamically manages a plurality of objects (). Each object () has a communication device () placed within or in close proximity to the object () for communicating a plurality of object information (). A group controller () communicates with the communication device () and takes over responsibility for communication within the communication system () for the communication device () when the object location () comes within a communication range of the group controller ().

Communication system for dynamic management of a plurality of objects and method therefor

A paging receiver device and method are disclosed in which analog information transmitted from an external source such as a paging transmitter are received and decoded. The analog information includes at least one voice message. The voice message is recovered, digitized, and stored in one of a plurality of message slots in a memory of the paging receiver. In response to a paging user's request, the digitized stored message is recalled from memory, reconverted from digital information to analog information, and used to produce audible voice information being a replica of the original analog voice message.

Digitized stored voice paging receiver

An adaptive lock time controller for a phase locked loop having dividers for generating first and second loop timing signals, a phase detector, a voltage controlled oscillator, and a charging circuit for generating at least a first control signal for converging the output frequency to one or more predetermined frequency channels and a second control signal for maintaining the output frequency substantially constant, comprises a synchronization generator, a phase lock detector, and a control signal selector. The synchronization generator is responsive to the phase detector for synchronizing the phase lock detector. The phase lock detector detects phase locked and unlocked conditions by generating a count representative of the phase difference between the first and second loop timing signals. When the count generated exceeds a predetermined count, a phase locked condition exists, otherwise the loop is unlocked. The control signal selector selects the first control signal during the predetermined time interval when the phase unlocked condition is detected, and the second control signal when the phase locked condition is detected.

Adaptive lock time controller for a frequency synthesizer and method

A built in test circuit within a frequency synthesizer for use in selective call radio receivers provides a selectable one of a plurality of internal signals as a test signal for diagnosing the frequency synthesizer's output in real time.

Diagnostic mode for a frequency synthesizer

A paging receiver has a synthesizer for governing the receive frequency. The paging receiving further has characteristics which are varied in response to the receive frequency. These characteristics include varying the bandwidth of a loop filter within a phase lock loop within the synthesizer as well as varying the time in which a detector circuit used to extract a DC level from a recovered audio signal is disabled. Furthermore, the bandwidth of the loop filter is varied in response to switching from a first receive frequency to a second receive frequency in order to provide for either a uniform frequency lock time or for a rapid frequency lock time. Furthermore, the time in which the detector circuit is disabled is correspondingly changed.

Synthesized selective call receiver having variable characteristics

An apparatus is described for the dual modulus prescaling of a high frequency signal. The apparatus comprises a dual modulus divider, second divider, synchronization circuit for providing a first modulus control signal to the dual modulus divider, and means for coupling the output of the second divider to the input of the synchronization circuit when a second modulus control signal is in a first state.

High speed prescaler

A high speed CMOS divide by 4/5 prescaler circuit comprises first, second, third, fourth, and fifth inverter stages. When a modulas control signal is low, the prescaler operates as five clocked inverters in series having an output which is fed back to the input of the initial stage. That is, the circuit operates as a five stage clocked ring oscillator wherein only one output changes on each clock edge. When a modulas control signal is high indicating that a divide by four is desired, the counter operates as a five stage ring oscillator for seven clock edges. On the eighth edge, feed forward circuitry forces the last three stages to change states simultaneously.

A method of and apparatus for automatically selecting one of first and second loop bandwidth states of a phase lock loop circuit of a frequency synthesizer. The phase lock loop circuit is governed by a reference frequency signal and a feedback frequency signal to adjust the frequency of the synthesized frequency signal to a frequency channel setting. Each of the reference and feedback frequency signals include one phase indication per frequency period. The feedback frequency signal is phase and frequency representative of the synthesized frequency signal. The loop bandwidth of the phase lock loop circuit is automatically switched from the first to the second state based on an initial occurrence of three successive phase indications of a selected one of the reference and feedback frequency signals between successive phase indications of the other, and automatically switched back from the second to the first state based on an initial occurrence of two successive phase indications of the other frequency signal between successive phase indications of the selected frequency signal.

Frequency synthesizer with improved automatic control of loop bandwidth

A frequency synthesizer which has at least one programmably characterized phase lock loop circuit includes a buffer memory and an interface controller responsive to operational codes received from a central controller to direct transfer of data words for characterization of the phase lock loop circuit among the at least one phase lock loop circuit, the buffer memory, and the central controller. In one embodiment, the transfer of data words between the central controller and phase lock loop circuit or buffer memory are performed serially in accordance with a prespecified protocol and governed by a clock signal generated by the central controller. Data word transfers between the buffer memory and at least one phase lock loop circuit may also be performed serially in accordance with a prespecified protocol, but may be governed autonomously by an internal clock signal generated by the frequency synthesizer.

Frequency synthesizer with an interface controller and buffer memory

A frequency synthesizer which includes at least one phase lock loop operative in a selected loop bandwidth state includes a dynamically programmable control circuit for setting the frequency range of its selected loop bandwidth state. In another aspect, the frequency synthesizer may include a plurality of phase lock loop circuits; and a common bias circuit programmably operative to generate at least one bias signal which is coupled commonly to the plurality of phase lock loop circuits for setting a common frequency range for the loop bandwidth states of all of the phase lock loop circuits. In still another aspect, the frequency synthesizer includes a phase lock loop circuit; and a bias circuit programmably operative to generate at least one bias signal which is coupled to the phase lock loop circuit for setting a reference frequency range of the loop bandwidth states thereof, the phase lock loop circuit being dynamically programmable to vary the frequency range settings of the loop bandwidth states in relation to the reference frequency range set by the bias circuit.

Frequency synthesizer with dynamically programmable frequency range of

A dual bandwidth crystal controlled oscillator is described having a first transconductance amplifier providing sufficient gain to maintain oscillation with an oscillator crystal at a minimum current drain. A second transconductance amplifier is provided which can be selectively coupled to the first transconductance amplifier, thereby augmenting the gain of the first transconductance amplifier to provide the capability for rapid oscillator start-up following battery saver operation. The dual bandwidth crystal controlled oscillator can be utilized in conventional oscillator and frequency synthesizer applications.

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Coconut Creek, FL, United States of America

Omid Tahernia