Intel Corporation

Omer Vikinski

Efraim Rotem

Zeev Sperber

Doron Rajwan

Dan Baum

Igor Yanover

Kosta Luria

Gabi Malka

Gavri Berger

Ronny Korner

Assaf Ganor

Noam Winer

In one embodiment, a processor includes: a power switcher circuit to receive a first voltage and charge at least one charge storage device with the first voltage in a first phase and output charge in a second phase; a selection circuit coupled to the power switcher circuit to couple the output charge to a selected one of a plurality of load circuits responsive to a control signal; and a control circuit to generate the control signal based at least in part on a comparison of a feedback voltage of a rail coupled to the selected load circuit to a reference voltage. Other embodiments are described and claimed.

Integrating a power arbiter in a processor

A processor and method are described for performing proactive throttling of execution unit ports. For example, one embodiment of a processor core comprises: a plurality of execution unit ports within an execution stage of the processor core; a scheduler unit to schedule execution of a plurality of operations to the plurality of execution unit ports; and proactive throttling logic to limit acceleration of execution of the operations by the ports to an acceleration level which does not result in significant power supply droops.

Method and apparatus for proactive throttling for improved power transitions in a processor core

Methods, apparatuses, and systems for managing power of a processing unit are described herein. Some embodiments include determining a voltage variation of a subset of current components of a current consumed by a processing unit. Other embodiments include detecting architectural events on a processing core of the processing unit and instituting various actions to reduce an input rate of instructions to the core. Other embodiments may be described and claimed.

Power management for processing unit

An apparatus that includes a driver circuit and an active load circuit coupled to an output of the driver circuit. The active load circuit is configured to actively adjust the slew rate of a signal outputted by the driver circuit.

Stable delay buffer

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Haifa, Israel

Omer Vikinski