International Business Machines Corporation

Omer Heymann

Amira Rozenfeld

Todd Alan Christensen

Elizabeth Lair Gerhard

Moshe Leibowitz

Alex Raphayevich

Lidor Goren

Gil Noy

Maya Speiser

Niv Amit

Ronit Bustin

Eric Francis Robinson

Nadav Levison

Haining S Yang

Robert C Wong

Amit Golander

Jason Alan Cox

Noam Jungmann

Elazar Kachir

Kevin C Lin

Limor Plotkin

Udi Nir

Dana Bar-Niv

A novel and useful cost effective mechanism for detecting the livelock/starvation of transactions in a ring shaped interconnect that utilizes minimal logic resources. Rather than monitor all transactions concurrently in the ring, the mechanism monitors only a single transaction in the ring. A sampling point is located at a point in the ring which contains a set of N latches. If the monitored transaction is not being starved, it is released and the detection logic moves on the next candidate transaction in round robin fashion. If the monitored transaction passes the sampling point a threshold number of times, it is deemed to be starved and a starvation prevention handling procedure is activated. By traversing the entire ring a single transaction at a time, all starving transactions will eventually be detected with an upper limit on the detection time of O(N).

Livelock prevention mechanism in a ring shaped interconnect utilizing round robin sampling

A method of increasing a drain to source voltage measured at an access pass-gate to a SRAM circuit in a SRAM memory array, including increasing a low voltage from a low voltage source powering said SRAM circuit, and increasing a high voltage from a high voltage source powering the SRAM circuit.

Boost cell supply write assist

Methods and apparatuses are disclosed for direct access to cache memory. Embodiments include receiving, by a direct access manager that is coupled to a cache controller for a cache memory, a region scope zero command describing a region scope zero operation to be performed on the cache memory; in response to receiving the region scope zero command, generating a direct memory access region scope zero command, the direct memory access region scope zero command having an operation code and an identification of the physical addresses of the cache memory on which the operation is to be performed; sending the direct memory access region scope zero command to the cache controller for the cache memory; and performing, by the cache controller, the direct memory access region scope zero operation in dependence upon the operation code and the identification of the physical addresses of the cache memory.

Direct access to cache memory

A novel and useful mechanism for reducing current leakage in a static random access memory array which significantly reduces the power requirements of the memory array. The method enables the steady state of all local and global bit lines in an SRAM array to be discharged during both active and inactive modes. The memory array includes memory cells having an N channel field effect transistor read stack. A mechanism is provided to evaluate data from memory cells where the steady state of local and global read bit lines is discharged.

Apparatus for and method of current leakage reduction in static random access memory arrays

A method and apparatus implementing domino static random access memory (SRAM) leakage current reduction include a local evaluation circuit coupled to true and complement bit lines of a pair of local SRAM cell groups, receives precharge signals and provides an output connected to a global dot line. A sleep input is applied to SRAM sleep logic and a write driver including sleep control. Data true and data complement outputs of the write driver are forced to a respective selected level to discharge the bit lines and global dot lines when the sleep input transitions high. Discharging the bit lines and global dot lines is implemented through gating in the write driver without requiring any additional devices in the local evaluation circuit.

Apparatus for implementing domino SRAM leakage current reduction

Method for implementing domino SRAM leakage current reduction

A method is provided for designing an integrated circuit. The method includes inserting wire model objects into the schematic of said circuit based on sizing and placement of components of the circuit, and performing an early timing analysis on said schematic. The steps of inserting and performing are repeated after re-sizing and/or re-placing the components if early timing analysis fails.

Method and system for enhancing circuit design process

The present invention is a method and system for modeling wiring routing in circuit design. According to some embodiments, the wire model objects ('WMO') may be inserted into the wiring routing on a 'WMO-per-segment' basis. According to some other embodiments, the wire model objects may be inserted into the wiring routing per groups of sequential segments. The entire wiring routing geometry may constitutes one group, and a wire model object may be inserted between the source point(s) and the target points based on the longest path in the routing geometry. An insertion rule may be selected based on any combination of the following factors: segment length, total path length, spacing between adjacent segments, wire metal and wire width. A wire model object may be selected from a group consisting of: {'C'; one &#x201c;RC&#x201d; arrangement; 'n' times &#x201c;&#x3a0;&#x201d;-type filter arrangement, wherein n=1, 2, 3, . . . , }. Several length ranges may be predefined to associate each segment, or path, with a particular type of wire model object.

Method and system for modeling wiring routing in a circuit design

The present invention is a method and system for schematically embedding wire model objects into a schematic design of an integrated circuit. The method includes estimating a wiring routing geometry for each signal path in the circuit, selecting one or more cascading wire model objects ('WMOs') for each segment in each geometry, and substituting each signal path with the respective one or more WMOs.

Method and system for embedding wire model objects in a circuit schematic design

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Moshav Tzofit, Israel

Omer Heymann