Western Digital Technologies, Inc.

Sandisk Technologies Inc.

Omer Fainzilber

Eran Sharon

Stella Achtenberg

Alexander Bazarsky

Ran Zamir

Dudy David Avraham

Ariel Navon

Idan Alrod

Ofir Pele

Yehuda Hahn

Simon Litsyn

Tz-Yi Liu

Idan Goldenberg

David Gur

Tianhong Yan

David Robison Hall

Yoav Weinberg

Karin Inbar

Mark Shlick

Ishai Ilani

Alex Bazarsky

Xinmiao Zhang

Alon Eyal

Yoav Markus

Yan Dumchin

Asaf Gueta

Yuri Ryabinin

Nika Yanuka

Eran Banani

Micha Yonin

Igal Mariasin

Gilat Flaishman

Arie Star

Tommer Kuper Lotan

Eyall Shadmi

Sanel Alterman

A multi-gear ECC decoder includes a high power decoder and a low power decoder. In order to significantly reduce the decoding time for high-BER codewords using a slow high power decoder, rather than decoding codewords in either slow high power or fast low power, a controller switches between slow high power decoding and fast low power decoding during the decoding process. The controller first will determine, based on a predetermined factor, whether to start decoding in slow high power or fast low power. Once a decoding power is determined, then the decoding will begin. During the decoding process the decoding transitions from a first power lever decoder to a second power level decoder. The decoding will continue in the second decoding power level after the transition, until the decoding is completed or if another switch needs to occur for insufficient decoding.

ML assisted dynamic decoding gear selection

The present disclosure generally relates to data storage devices, such as solid state drives. A data storage device includes a controller, one or more volatile memory locations, and one or more non-volatile memory locations. Computations, including reinforcement learning algorithms, may be completed by the controller using the one or more non-volatile memory locations. Data associated with reinforcement learning is stored in a table on one or more planes of the non-volatile memory, where the results from the computations update the table with the relevant values. The data in the table are aligned to one or more wordlines, such that sensing the wordline senses all the data stored in the table.

Memory device with reinforcement learning with Q-learning acceleration

A storage device includes a memory die and a controller. The controller identifies a dirty block that was subject to an interrupted I/O operation and performs a coarse inspection of the dirty block. Each iteration of the coarse inspection includes: requesting first bytes of a current page of the dirty block; receiving contents of the first bytes from the at least one memory die; and evaluating a state of the current page based on the contents of the first bytes. The controller also determines an initial last good page based on the coarse inspection and performs a fine inspection of at least one page based on a second number of bytes greater than the first number of bytes. The fine inspection validates the initial last good page and identifies the initial last good page as an actual last good page of the dirty block.

Systems and methods for improving find last good page processing in memory devices

Advanced ultra-low power error correcting codes are generated using soft quantization and lattice interpolation based on clock and Syndrome Weight. Reinforcement learning may be used to generate threshold values for flipping bits for low density parity check Ultra-Low Power error correction codes. The threshold values can be generated offline and downloaded to a storage device or generated while the storage device is in use.

Advanced ultra low power error correcting code encoders and decoders

A data storage device includes a hard disk drive coupled to a printed circuit board (PCB), a volatile memory device coupled to the PCB, a non-volatile memory device coupled to the PCB, and a controller coupled to the PCB, such that the controller is in communication with the hard disk drive, the volatile memory device, and the non-volatile memory device. The controller is configured to identify patterns and/or structures of metadata for the hard disk drive, perform one or more of the following to the metadata to tailor the metadata: data shaping, content aware decoding, adaptive data trimming, and/or adaptive metablock sizing, and write the tailored metadata to the non-volatile memory device. The metadata is at least one of repeatable run out metadata, positioning error signal metadata, adjacent track interference metadata, and/or emergency power off metadata.

Methods for writing HDD metadata in NAND flash

A method and apparatus for content aware decoding utilizes a pool of decoders shared data statistics. Each decoder generates statistical data of content it decodes and provides these statistics to a joint statistics pool. As codewords arrive at the decoder pool, the joint statistics are utilized to estimate or predict any corrupted or missing bit values. Codewords may be assigned to a specific decoder, such as a tierdecoder, a tierdecoder, or a tierdecoder, based on a syndrome weight or a bit error rate. The assigned decoder updates the joint statistics pool after processing the codeword. In some embodiments, each decoder may additionally maintain local statistics regarding codewords, and use the local statistics when there is a statistically significant mismatch between the local statistics and the joint statistics pool.

Content aware decoding using shared data statistics

A method of temperature compensation to read a flash memory device includes determining a state of the flash memory device. An action is selected with a maximum Q-value from a Q-table for the current state during exploitation. A read operation of a code word from the flash memory device is conducted using one or more parameters according to the selected action. The code word is decoded with an error correction code (ECC) process.

Machine learning for temperature compensation

A memory controller including, in one implementation, a memory interface and a control circuit. The memory interface is configured to receive a punctured codeword read from a non-volatile memory. The control circuit is configured to determine error probability values for a plurality of check nodes associated with a punctured bit included in the punctured codeword. The control circuit is also configured to determine an error probability value for the punctured bit based on the error probability values for the plurality of check nodes associated with the punctured bit and a variable degree associated with the punctured bit. The control circuit is further configured to determine a log likelihood ratio (LLR) value for the punctured bit based on the error probability value for the punctured bit. The control circuit is also configured to decode the punctured codeword using the LLR value for the punctured bit.

Soft information for punctured bit estimation in a data storage device

A memory controller that includes, in one implementation, a memory interface and a controller circuit. The memory interface is configured to interface with a non-volatile memory. The controller circuit is configured to receive a skewed codeword read from the non-volatile memory. The controller circuit is also configured to scan the skewed codeword by inserting or removing a quantity of bits at different locations in the skewed codeword and determining resulting syndrome weights of the skewed codeword. The controller circuit is further configured to determine an adjusted codeword by inserting or removing the quantity of bits at one of the different locations in the skewed codeword which results in a smallest syndrome weight. The controller circuit is also configured to decode the adjusted codeword.

Data storage device with syndrome weight minimization for data alignment

A method and apparatus for obtaining data from a memory, estimating a probability of data values of the obtained data based on at least one of a source log-likelihood ratio and a channel log-likelihood ratio, wherein each bit in the obtained data has an associated log-likelihood ratio, determining at least one data pattern parameter for the data and performing a decoding process using the at least one data pattern parameters to determine a decoded data set.

Content aware decoding method and system

An error correcting code (ECC) decoder for a non-volatile memory device is configured to decode data stored by the non-volatile memory device using a parity check matrix with columns of different column weights. The ECC decoder is further configured to artificially slow processing of one or more of the columns of the parity check matrix in response to column weights for the one or more columns satisfying a threshold.

Decoder for irregular error correcting codes

A storage system and method for predictive block allocation for efficient garbage collection are provided. One method involves determining whether a memory in a storage system is being used in a first usage scenario or a second usage scenario; in response to determining that the memory is being used in the first usage scenario, using a first block allocation method; and in response to determining that the memory is being used in the second usage scenario, using a second block allocation method, wherein the first block allocation method allocates blocks that are closer to needing garbage collection than the second block allocation method.

Storage system and method for predictive block allocation for efficient garbage collection

Examples described herein relate generally to content aware bit flipping decoders. An example device includes a decoder. The decoder is configured to: process one or more flip thresholds based on statistics of data to be decoded; and perform a bit flipping algorithm on the data using the one or more processed flip thresholds. Other examples relate to methods of processing one or more flip thresholds based on statistics of data to be decoded and performing a bit flipping algorithm on the data using the one or more processed flip thresholds.

Content aware bit flipping decoder

A memory system configured to decode a data set may pause a convergence process to update reliability metric values. The memory system may utilize a positive feedback system that updates the reliability metric values by analyzing current a posteriori reliability metric values to calculate average estimated reliability characteristic values associated with a memory error model. The updates to the reliability metric values may provide increased error correction capability and faster decoding.

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Even Yehuda, Israel

Omer Fainzilber