Freescale Semiconductor,inc.

Other

Omar Zia

Ruiqi Tian

Nigel Graeme Cave

Edward Outlaw Travis, Jr

Venkat Kolagunta

Lawrence Cary Gunn, Iii

Bich-Yen Nguyen

Mariam G Sadaka

Marius K Orlowski

Sinan Goktepeli

Brian A Winstead

Da Zhang

Byoung W Min

Narayanan C Ramani

Hsiao-Hui Chen

A method for making a semiconductor device is provided which comprises (a) creating a first mask for the epitaxial growth of features in a semiconductor device, said first mask defining a set of epitaxial tiles (); (b) creating a second mask for defining the active region of the semiconductor device, said second mask defining a set of active tiles (); and (c) using the first and second masks to create a semiconductor device.

Integrated assist features for epitaxial growth

A method for making a semiconductor device is provided which comprises (a) creating a data set () which defines a set of tiles for a polysilicon deposition process; (b) deriving a polysilicon deposition mask set () from the data set, wherein the polysilicon deposition mask set includes a plurality of polysilicon tiles (); (c) deriving an epitaxial growth mask set () from the data set, wherein the epitaxial growth mask set includes a plurality of epitaxial tiles (); and (d) using the polysilicon deposition mask set and the epitaxial growth mask set to make a semiconductor device (); wherein the epitaxial growth mask set is derived from the data set by using at least a portion of the tile pattern defined in the data set for at least a portion of the tile pattern defined in the epitaxial deposition mask set.

A method for forming a semiconductor device includes providing a semiconductor substrate having a first region and a second region. The first region has one or more first elements and the second region has one or more second elements. The first elements are different from the second elements. A tile location and a first tile surface area for a tile feature on the semiconductor device is defined. An active semiconductor layer is formed over both the first region and the second region of the semiconductor substrate. A first trench is formed in the active semiconductor layer at the tile location using a negative tone mask. The first trench has a first depth and forms at least a portion of the tile feature. A second trench is formed in the active semiconductor layer using a positive tone mask. The second trench has a second depth different than the first depth.

Semiconductor device having tiles for dual-trench integration and method therefor

A method for making a semiconductor device is provided which comprises (a) creating a first data set () which defines a first set of tiles () for a trench chemical mechanical polishing (CMP) process; (b) deriving a first trench CMP mask set () and a first epitaxial growth mask set () from the first data set, wherein the first epitaxial growth mask set is derived from the first data set by removing a subset () of the tiles defined by the first data set and incorporating the subset of tiles into the first epitaxial growth mask set; and (c) reconfiguring the first trench CMP mask set to account for the first epitaxial growth mask set, thereby defining a second trench CMP mask set ().

Integrated assist features for epitaxial growth bulk tiles with compensation

A process of forming an electronic device can include forming an insulating layer over first and second active regions, and a field isolation region. The process can also include forming a seed layer and exposing the first active region. The process can further include selectively forming a first and second semiconductor layer over the first active region and the seed layer, respectively. The first and second semiconductor layers can be spaced-apart from each other. In one aspect, the process can include selectively forming the first and second semiconductor layers simultaneously at a substantially same point in time. In another aspect, an electronic device can include first and second transistor structures separated by a field isolation region and electrically connected by a conductive member. A semiconductor island, designed to be electrically floating, can lie between the conductive member and the base layer.

Process of forming an electronic device including a seed layer and a semiconductor layer selectively formed over the seed layer

A method for making a semiconductor device is provided which comprises (a) creating a first data set () which defines a first set of tiles () for a trench chemical mechanical polishing (CMP) process; (b) deriving a first trench CMP mask set () and at least one epitaxial growth mask set () from the first data set, wherein the at least one epitaxial growth mask set corresponds to tiles () present on first () and second () distinct semiconductor surfaces; (c) reconfiguring the first trench CMP mask set to account for the at least one epitaxial growth mask set, thereby defining a second trench CMP mask set (), wherein the second trench CMP mask set defines a set of trench CMP tiles; and (d) using the second trench CMP mask set to make a semiconductor device.

Integrated assist features for epitaxial growth bulk/SOI hybrid tiles with compensation

A semiconductor process and apparatus provide a planarized hybrid substrate () by exposing a buried oxide layer () in a first area (), selectively etching the buried oxide layer () to expose a first semiconductor layer () in a second smaller seed area (), and then epitaxially growing a first epitaxial semiconductor material from the seed area () of the first semiconductor layer () that fills the second trench opening () and grows laterally over the exposed insulator layer () to fill at least part of the first trench opening (), thereby forming a first epitaxial semiconductor layer () that is electrically isolated from the second semiconductor layer (). By forming a first SOI transistor device () over a first SOI layer () using deposited (100) silicon and forming first SOI transistor () over an epitaxially grown (110) silicon layer (), a high performance CMOS device is obtained.

Dual surface SOI by lateral epitaxial overgrowth

A semiconductor device is formed as part of an integrated circuit. The semiconductor device, which is formed in an active semiconductor layer, is surrounded by a guardian that provides a diffusion barrier against contaminants and also provides assistance in avoiding dishing above the semiconductor device during chemical mechanical polishing. The dielectric that is above the semiconductor device and inside the guardian is etched to form an opening that receives one of an optical fiber, an electromagnetic signal source, or an electromagnetic signal load. The remaining dielectric is in layers that are of substantially uniform thickness. The guardian is built up in layers that are part of a normal integrated circuit process. These include contact layers, via layers, and interconnect layers.

Method of forming a semiconductor device

A method of integrating a non-MOS transistor device and a CMOS electronic device on a semiconductor substrate includes forming openings within an active semiconductor layer in first and second regions of a semiconductor substrate. The first region corresponds to a non-MOS transistor device portion and the second region corresponds to a CMOS electronic device portion. The openings are formed using a dual trench process, forming openings or shallow trenches in the non-MOS transistor device portion to a first depth, and openings in the CMOS electronic device portion to a second depth greater than the first depth. The method further includes forming first and second non-MOS transistor device implant regions within the active semiconductor layer underlying the shallow trenches in the non-MOS transistor device portion, forming first and second low dose non-MOS transistor device well regions in the active semiconductor layer disposed in-between the first and second shallow trenches, forming high dose non-MOS transistor device connectivity regions, forming a salicide blocking layer overlying at least the first and second low dose non-MOS transistor device well regions, forming first and second non-MOS transistor device contact regions, and saliciding the semiconductor substrate, wherein the salicide blocking layer prevents salicidation of the first and second low dose non-MOS transistor device well regions.

In one embodiment, a method for forming a semiconductor device is described. A semiconductor substrate has a first portion and a second portion. A first dielectric layer formed over the first portion of the semiconductor substrate and a second dielectric layer is formed over the second portion of the semiconductor substrate. A cap that may include silicon, such as polysilicon, is formed over the first dielectric layer. A first electrode layer is formed over the cap and a second electrode layer is formed over the second dielectric.

Method of forming a semiconductor device and structure thereof

A method for integrating an optical device and an electronic device on a semiconductor substrate comprises forming openings within an active semiconductor layer in a first region of the semiconductor substrate, wherein the first region corresponds to an electronic device portion and the second region corresponds to an optical device portion. A semiconductor layer is epitaxially grown overlying an exposed active semiconductor layer in the second region, the epitaxially grown semiconductor layer corresponding to an optical device region. At least a portion of an electronic device is formed on the active semiconductor layer within the electronic device portion of the semiconductor substrate. The method further includes forming openings within the epitaxially grown semiconductor layer of the optical device portion of the semiconductor substrate, wherein the openings define one or more features of an optical device.

Method of integrating optical devices and electronic devices on an integrated circuit

A method for integrating first and second type devices on a semiconductor substrate includes forming openings within an active semiconductor layer of a dual semiconductor-on-insulator in first and second regions of the semiconductor substrate. First and second non-MOS transistor device implant regions are formed within portions of an intermediate semiconductor layer underlying first and second openings, respectively, in a first device portion, filled with a fill material and planarized. A top surface portion of the active semiconductor layer disposed in-between the first and second openings is exposed, first and second low dose non-MOS transistor device well regions are formed in respective first and second portions of the intermediate semiconductor layer underlying a region in-between the first and second openings. The method further includes forming a salicide blocking layer, forming first and second contact vias within the fill material of the first and second openings, respectively, exposing a portion of the underlying intermediate semiconductor layer, forming first and second non-MOS transistor device contact regions in exposed portions of the intermediate semiconductor layer, and saliciding the semiconductor substrate, the salicide blocking layer preventing salicidation of the first and second low dose non-MOS transistor device well regions.

A semiconductor structure has a waveguide a transistor on the same integrated circuit. One trench isolation technique is used for defining a transistor region and another is used for optimizing a lateral boundary of the waveguide. Both the waveguide and the transistor have trenches with liners that can be separately optimized. The transistor has a salicide for source/drain contacts. During this process, a salicide block is used over the waveguide to prevent salicide formation in unwanted areas of the waveguide. The depth of the trench for the waveguide can be lower than that of the trench for the transistor isolation. Trench isolation depth can be set by an etch stop region that can be either a thin oxide layer or a buffer layer that is selectively etchable with respect to the top semiconductor layer and that can be used as a seed layer for growing the top semiconductor layer.

Growing community of inventors

Austin, TX, United States of America

Omar Zia