Nxp B.v.

Koninklijke Philips Corporation N.v.

Om Prakash Gangwal

Pieter Van Der Wolf

Christiaan Varekamp

Abraham Karel Riemens

Anteneh Alemu Abbo

Richard Petrus Kleihorst

Josephus Theodorus Johannes Van Eijndhoven

Eric Peter Funke

Martijn Rutten

Evert-Jan Daniël Pol

Mickael Stephane Bernard George Bouvier

The present invention relates to an image enhancement unit and a method of enhancing a first structure (S) of samples into a second structure (S) of samples, the first and the second structure both representing a first property of a scene and having a first resolution, based on a third structure (S) of samples representing a second property and having the first resolution, the first property and the second property respectively representing different properties of substantially the same scene. The method comprising generating a fourth structure (S) of samples representing the first property, the fourth structure (S) of samples having a second resolution lower than the first resolution, by down-scaling first samples of the first structure (S) of samples to form the samples of the fourth structure (S) of samples. The method further comprising up-scaling the fourth structure (S) of samples representing the first property, into the second structure (S) based on the third structure (S) of samples, the up-scaling comprising assigning weight factors to respective samples of the fourth structure (S) of samples based on samples of the third structure (S) of samples; and computing samples of the second structure (S) of samples using the samples of the fourth structure (S) of samples and their respectively assigned weight factors. The invention further relates to an image-processing unit comprising an image enhancement unit according to the invention as well as to a computer program product.

Image enhancement

A processing element () forming part of a parallel processing array such as SIMD comprises an arithmetic logic unit (ALU) (), a multiplexer (MUX) (), an accumulator (ACCU) () and a flag register (FLAG) (). The ALU is configured to operate on a common instruction received by all processing elements in the processing array. The processing element () further comprises a storage element (SE) (), which supports the processing of local customized (i.e. data dependent) processing in the processing element (), such as lookup table operations and the storing local coefficient data.

Parallel processing array

Video stream processing, such as processing that includes MPEG decoding an subsequent post-processing involves using signal processing circuitry () to execute a first and a second video stream processing function. The first video stream processing function produces frame data of successive video frames in a temporally ordered output sequence of frames. The second video stream processing function uses the frame data in an ordered input sequence of frames that differs from the output sequence, for example because later P-frames are needed to decode B frames. The frame data is buffered between application of the first and second video processing function to the frame data. A first and a second. buffer memory () are used. The first buffer memory () is coupled to the signal processing circuitry via a shareable channel () such as an external IC terminals, but the processing circuitry does not use the shareable channel () to access the second buffer memory (). The second video processing function reads frame data from first and second ones of the frames selectively from the first and second buffer memory () respectively. The second ones of the frames occur in the same temporal order in both the input and output sequence. The first ones of the frames contain at least all particular frames whose position relative to the second ones of the frames in the output sequence differs from the position of the particular frames relative to the second ones of the frames in the input sequence.

Video processing circuit and method of video processing

Aspects involve effectively separating communication hardware in a data processing system by introducing a communication device for each processor. By introducing this separation the processors can concentrate on performing their function-specific tasks, while the communication device provide the communication support for the respective processor. Accordingly, in certain embodiments, a data processing system is provided with a computation, a communication support and a communication network layer.

Data processing system having multiple processors and a communications means in a data processing system

A processing circuit executes a data producing process and a data consuming process. The data producing process produces a stream of data, the data consuming process consumes the stream of data concurrently with production of the stream. A first-in first-out buffer passes data from the stream between the data producing process and the data consuming process. The buffer comprises buffer memory, the buffer writes data-items from the stream in circular fashion into the buffer memory. A consuming process interface is arranged to process a command for making a data grain from the stream available to the data consuming process. The interface responds to the command by testing whether addresses of data within the grain to which access has to be gained wrap around in the circular FIFO buffer. The interface copies the grain from the FIFO buffer to the auxiliary memory region, on condition that the addresses wrap around, so that the wrap around is eliminated in the copied grain, The interface returns an indication to the consuming process to read the grain from the FIFO buffer when the addresses do not wrap around inside the grain, or an indication to read from the auxiliary memory region, when the addresses wrap around.

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Eindhoven, Netherlands

Om Prakash Gangwal