Intel Corporation

Om Ji Omer

Sreenivas Subramoney

Dipan Kumar Mandal

Gurpreet Singh Kalsi

Anirud Thyagharajan

Prashant Laddha

Kamlesh R Pillai

Gopi Neela

Biji George

Belliappa Manavattira Kuttanna

Lance E Hacking

Avishaii Abuhatzera

Santhosh Kumar Rethinagiri

Yuval Amizur

Leor Banin

Anant V Nori

Nir Dvorecki

Cormac Brick

Shengbo Xu

Chulong Chen

Saiveena Kesaraju

Shankar Balachandran

Joydeep Rakshit

Srivatsa Rangachar Srinivasa

Pradyumna S Singh

Mahesh Mamidipaka

Benjamin Ummenhofer

Srivatsava Jandhyala

Akshay Krishna Ramanathan

Anish N K

Wenling Margaret Huang

Nagadastagiri Reddy C

Krishnan Ananthanarayanan

Rahul Bera

Ivan Simões Gaspar

Hao Chen

Meenal Kudalkar

Ritwika Chowdhury

Saurabh Jain

An embodiment of an apparatus comprises a hardware accelerator to perform a three-dimensional (3D) point cloud data access operation, and circuitry coupled to the hardware accelerator to control the hardware accelerator to perform the 3D point cloud data access operation in response to a request. Other embodiments are disclosed and claimed.

Point cloud adjacency-map and hash-map accelerator

Apparatus and method for leveraging simultaneous multithreading for bulk compute operations. For example, one embodiment of a processor comprises: a plurality of cores including a first core to simultaneously process instructions of a plurality of threads; a cache hierarchy coupled to the first core and the memory, the cache hierarchy comprising a Level 1 (L1) cache, a Level 2 (L2) cache, and a Level 3 (L3) cache; and a plurality of compute units coupled to the first core including a first compute unit associated with the L1 cache, a second compute unit associated with the L2 cache, and a third compute unit associated with the L3 cache, wherein the first core is to offload instructions for execution by the compute units, the first core to offload instructions from a first thread to the first compute unit, instructions from a second thread to the second compute unit, and instructions from a third thread to the third compute unit.

Method and apparatus for leveraging simultaneous multithreading for bulk compute operations

Exemplary embodiments maintain spatial locality of the data being processed by a sparse CNN. The spatial locality is maintained by reordering the data to preserve spatial locality. The reordering may be performed on data elements and on data for groups of co-located data elements referred to herein as 'chunks'. Thus, the data may be reordered into chunks, where each chunk contains data for spatially co-located data elements, and in addition, chunks may be organized so that spatially located chunks are together. The use of chunks helps to reduce the need to re-fetch data during processing. Chunk sizes may be chosen based on the memory constraints of the processing logic (e.g., cache sizes).

Methods, apparatus, and articles of manufacture to reorder N-dimensional sparse data into groups of data elements that can be collocated in a memory

According to various embodiments, a radar device is described comprising a processor configured to generate a scene comprising an object based on a plurality of receive wireless signals, generate a ground truth object parameter of the object and generate a dataset representative of the scene and a radar detector configured to determine an object parameter of the object using a machine learning algorithm and the dataset, determine an error value of the machine learning algorithm using a cost function, the object parameter, and the ground truth object parameter and adjust the machine learning algorithm values to reduce the error value.

High end imaging radar

Methods, apparatus, systems, and articles of manufacture are disclosed to improve in-memory multiply and accumulate operations. An example apparatus includes a first multiplexer in a subarray of memory, the first multiplexer to receive first values representative of a column of a lookup table (LUT) including entries to represent products of four-bit numbers and return second values from an intersection of a row and the column of the LUT based on a first element of a first operand; shift and adder logic in the subarray, the shift and adder logic to shift the second values based on at least one of the first element of the first operand or a first element of a second operand; and accumulation storage in the subarray, the accumulation storage to store at least the shifted second values.

Methods, apparatus, and articles of manufacture to improve in-memory multiply and accumulate operations

A computer model is trained to classify regions of a space (e.g., a pixel of an image or a voxel of a point cloud) according to a multi-label classification. To improve the model's accuracy, the model's self-confidence is determined with respect to its own predictions of regions in a training space. The self-confidence is determined based on the class predictions, such as a difference between the highest-predicted class and a second-highest-predicted class. When these are similar, it may reflect areas for potential improvement by focusing training on these low-confidence areas. Additional training may be performed by including modified training data in subsequent training iterations that focuses on low-confidence areas. As another example, additional training may be performed using the self-confidence to modify a classification loss used to refine parameters of the model.

Applying self-confidence in multi-label classification to model training

Systems, apparatuses and methods may provide for technology that decodes data via an instruction that indicates a number of rulebooks to be processed, an input feature size, an output feature size, and a plurality of feature map base addresses, rearranges spatially distributed voxel output feature maps in the decoded data based on weight planes, and performs a channel-wise multiply-accumulate (MAC) operation on the rearranged spatially distributed voxel output feature maps to obtain an output, wherein the channel-wise MAC operation is performed as partial accumulations by a plurality of processing elements.

Spatially sparse neural network accelerator for multi-dimension visual analytics

Techniques related to indirect sparse simultaneous localization and mapping (SLAM) are discussed. Such techniques include adaptively positioning a virtual camera relative to an estimated position of a physical camera within an environment to be mapped, projecting a depth error to an image plane corresponding to the adaptive camera position, and using the projected depth error to update a mapping of the environment.

Adaptive virtual camera for indirect-sparse simultaneous localization and mapping systems

An apparatus to facilitate accelerating neural networks with low precision-based multiplication and exploiting sparsity in higher order bits is disclosed. The apparatus includes a processor comprising a re-encoder to re-encode a first input number of signed input numbers represented in a first precision format as part of a machine learning model, the first input number re-encoded into two signed input numbers of a second precision format, wherein the first precision format is a higher precision format than the second precision format. The processor further includes a multiply-add circuit to perform operations in the first precision format using the two signed input numbers of the second precision format; and a sparsity hardware circuit to reduce computing on zero values at the multiply-add circuit, wherein the processor to execute the machine learning model using the re-encoder, the multiply-add circuit, and the sparsity hardware circuit.

Accelerating neural networks with low precision-based multiplication and exploiting sparsity in higher order bits

A disclosed apparatus to multiply matrices includes a compute engine. The compute engine includes multipliers in a two dimensional array that has a plurality of array locations defined by columns and rows. The apparatus also includes a plurality of adders in columns. A broadcast interconnect between a cache and the multipliers broadcasts a first set of operand data elements to multipliers in the rows of the array. A unicast interconnect unicasts a second set of operands between a data buffer and the multipliers. The multipliers multiply the operands to generate a plurality of outputs, and the adders add the outputs generated by the multipliers.

Methods, apparatus, articles of manufacture to perform accelerated matrix multiplication

An example apparatus for selecting keypoints in image includes a keypoint detector to detect keypoints in a plurality of received images. The apparatus also includes a score calculator to calculate a keypoint score for each of the detected keypoints based on a descriptor score indicating descriptor invariance. The apparatus includes a keypoint selector to select keypoints based on the calculated keypoint scores. The apparatus also further includes a descriptor calculator to calculate descriptors for each of the selected keypoints. The apparatus also includes a descriptor matcher to match corresponding descriptors between images in the plurality of received images. The apparatus further also includes a feature tracker to track a feature in the plurality of images based on the matched descriptors.

Selecting keypoints in images using descriptor scores

An embodiment of an image processor device includes technology to fetch a feature point data set from outside a local memory, locally store three or more fetched feature point data sets in the local memory, compute orientation information for each fetched feature point data set, compute first descriptor information based on the computed orientation information and a first locally stored feature point data set in parallel with a fetch and local store of a second feature point data set in the local memory, and compute second descriptor information based on the computed orientation information and the second locally stored feature point data set in parallel with the compute of the first descriptor information. Other embodiments are disclosed and claimed.

Architecture to generate binary descriptor for image feature point

An example apparatus for tracking features in image data includes an image data receiver to receive initial image data corresponding to an image from a camera and store the image data a circular buffer. The apparatus also includes a feature detector to detect features in the image data. The apparatus further includes a feature sorter to sort the detected features to generate sorted feature points. The apparatus includes a feature tracker to track the sorted feature points in subsequent image data corresponding to the image received at the image data receiver. The subsequent image data is to replace the initial image data in the circular buffer.

Feature detection, sorting, and tracking in images using a circular buffer

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Bengaluru, India

Om Ji Omer