Telefonaktiebolaget Lm Ericsson (publ)

Olli Varkki

Marko Pessa

Harri Eksymä

Mikko Lintonen

Jukka Kohola

A method for controlling powering of a mobile platform comprising a first Finite State Machine (FSM) and a second FSM. The method comprises synchronizing the first FSM with the second FSM, wherein the first FSM is arranged on a first Integrated Circuit (IC) comprised in the mobile platform and configured to control a first Power Management Unit (PMU) arranged on the first IC, and wherein the second FSM is arranged on a second IC comprised in the mobile platform and configured to control a second PMU arranged on the second IC, whereby the first PMU and the second PMU are synchronized to operate simultaneously during rank-up and rank-down, thereby providing power control of the mobile platform.

Mobile platform and a method therein

A method for controlling powering of a mobile platformcomprising a first Finite State Machine (FSM)and a second FSM. The method comprises synchronizing the first FSM with the second FSM, wherein the first FSM is arranged on a first Integrated Circuit (IC)comprised in the mobile platform and configured to control a first Power Management Unit (PMU)arranged on the first IC, and wherein the second FSM is arranged on a second ICcomprised in the mobile platform and configured to control a second PMUarranged on the second IC, whereby the first PMU and the second PMU are synchronized to operate simultaneously during rank-up and rank-down, thereby providing power control of the mobile platform.

A clock generation circuit is operative to disable and enable a plurality of output clock signals while maintaining predetermined phase relationships between the clock signals. A reference clock signal is divided by a factor of at least two, to generate a master clock signal. A plurality of phase circuits, each independently enabled, generates a plurality of output clock signals by dividing the reference clock signal. The output clock signals have predetermined phase relationships relative to each other. Each phase circuit is enabled synchronously to a synchronization edge of the master clock signal. A synchronization circuit associated with each phase circuit ensures synchronization with the master clock signal by outputting a phase circuit enable signal only upon the conditions of a clock enable signal associated with the output clock being asserted and the receipt of a predetermined number of master clock signal synchronizing edges.

Growing community of inventors

Oulu, Finland

Olli Varkki