Texas Instruments Corporation

University of Toronto

Nxp B.v.

Eleappower Ltd.

Semiconductor Components Industries, LLC

Nxp Usa, Inc.

Other

Solantro Semiconductor Corp.

Altera Corporation

Havelaar Canada Industrial R & D Laboratory Ltd.

Olivier Trescases

Johan Tjeerd Strydom

Rajarshi Mukhopadhyay

Hendrik Johannes Bergveld

John M Pigott

Gerard Villar Piqué

Alaa Eldin Y El Sherif

Stefano Pietri

Jitendra Prabhakar Harshey

Mojtaba Ashourloo

Venkata Raghuram Namburi

Edevaldo Pereira Da Silva Junior

Shahab Poshtkouhi

Shuze Zhao

Zhe Gong

Nameer Ahmed Khan

Vaughn Betz

Peter Moens

Raymond Kenneth Orr

James Benson Bacque

Jaume Roig-Guitart

Wai Tung Ng

Matthias Rose

Jurgen Geerlings

Herbert De Vleeschouwer

David King Wai Li

Mohammad Shawkat Zaman

Oscar Igor Robles Palacios

Vaughan Betz

Ibrahim Ahmed Ibrahim

Rajarshi Mukhopdhyay

Ibrahim Ahmed

Miad Nasr

A method, power converter and controller are disclosed for controlling a power converter having a main converter connected between a first input voltage and a ground and having a main output at an output terminal, an auxiliary converter connected between a second input voltage and the ground and having an auxiliary output, an output capacitor connected between the main output terminal and a ground, and an auxiliary capacitor connected between the auxiliary output and the main output terminal; and a controller; the method comprising: operating the main converter at a first frequency, operating the auxiliary converter at a second frequency; controlling the main converter to control the voltage at the auxiliary output; and controlling the auxiliary converter to control the voltage at the main output.

Control of two-stage dc-dc converter

Disclosed are a controller and power converter having a main buck converter connected between a first input voltage and ground and having a main output, a bidirectional auxiliary converter connected between a second terminal and ground and having an auxiliary output connected to the main output, an output capacitor, and an auxiliary capacitor connected between the second terminal and the ground for providing a second terminal voltage at the second terminal; the controller comprising: first control circuit configured to operate the main converter at a first frequency; and second control circuit configured to operate the auxiliary converter at a higher frequency; the first control circuit being further configured to operate the main converter in dependence on the second terminal voltage; and the second control circuit being further configured to operate the auxiliary converter to control the voltage at the main output terminal.

Control of auxiliary-assisted DC-DC converter

When balancing cells in battery packs, the voltage induced by the balancing current across the parasitic wire resistance distorts the measured cell voltage, leading to inaccurate cell state estimation. A method and battery management system to extract a parasitic resistance of battery connection wires connecting a cell of a battery to a cell balancing circuit is disclosed. The parasitic wire resistances for a battery pack are extracted through the coordinated operation of a pack-level current source and cell-level balancing circuit. A voltage drop is imposed and measured across the parasitic resistances while maintaining zero current in the immediate battery cell. Maintaining zero current in the immediate battery cell avoids possible extraction error resulting from voltage drop across the battery cell impedance due to battery cell current flow.

Method and system for improved state estimation accuracy in battery management systems with cell balancing

In an embodiment, a HEMT is formed to have a main transistor having a main active area and a sense transistor having a sense active area. An embodiment may include that the main active area is isolated from the sense active area.

High electron mobility transistor

A power-hub for an electric vehicle and operating modes thereof are disclosed herein. The disclosed power-hub is designed to operate in the Vehicle-to Grid (V2G), Grid-to-Vehicle (G2V), Vehicle-to-Home (V2H), and Vehicle-to-Vehicle (V2V) operating modes. When operating in the V2V mode, the power-hub is configured to allow for sending DC power through a conventional AC power port, with all the associated ratings and constraints from the AC design, in order to achieve higher power transfer and efficiency for V2V operation. A digital Hysteretic Current Mode Control (HCMC) scheme is disclosed and the efficiency and loss distribution of four operating modes are disclosed for the power-hub: 1) DC-AC Boundary Conduction Mode (BCM), 2) DC-AC Continuous Conduction Mode (CCM)/BCM hybrid, 3) DC-DC BCM, and 4) DC-DC CCM. A low-frequency commutation scheme is also disclosed that allows for reducing the peak junction temperature.

Electric vehicle power-hub and operating modes thereof

In circuitry for measuring a voltage at a node, a capacitive divider is coupled to the node, wherein the capacitive divider provides a first output. A resistive divider is coupled to the node, wherein the resistive divider provides a second output.

Methods and circuitry for analyzing voltages

The present disclosure provides electrical architecture for electrochemical impedance spectroscopy (EIS). An EIS circuit comprises at least two current regulators and an electrical energy storage device, which are connected with one or more electrochemical cells in a configuration that decouples power flowing into the respective current regulators. The presence of the electrical energy storage device enables each regulator to operate simultaneously at lower power levels while inducing the desired EIS perturbation current. Operation at low power allows lower volume and cost for the same current compared to only dissipative or non-dissipative current regulators. Further, the electrical energy storage device allows the power flowing through the current regulators to be varied independently in order to achieve the desired EIS perturbation current while a minimum amount of heat is generated in the circuit, thus allowing the circuit to occupy minimal size and incur minimal cost.

Electrical architecture for electrochemical impedance spectroscopy

There are disclosed fault detection circuits and methods for an N-to-1 Dickson topology hybrid DC-DC power converter. A short circuit fault detection circuit comprises: first and second measuring circuits configured to measure first and second voltages, Vsw, Vsw, at the switching node in the first and second state; first and second calculation circuits configured to calculate first and second absolute error voltage as an absolute difference of the respective first and second voltages in one operating cycle (Vsw[n&#x2212;1], Vsw[n&#x2212;1]) and in a next subsequent operating cycle (Vsw[n], Vsw[n]); and first and second fault circuits configured to provide first and second fault outputs indicative of a fault in response to the respective first or second absolute error voltage exceeding a short-circuit-trip level. Open circuit fault detection circuits and methods are also disclosed.

Fault detection in hybrid DC-DC power convertors

Methods and circuitry for driving a device are disclosed. An example of the circuitry includes a voltage sensing circuit coupled to an input of a transistor, the voltage sensing circuit having a first output at a node, the voltage sensing circuit comprising a capacitive voltage divider, and a current sensing circuit coupled to the input of the transistor and to the voltage sensing circuit, the current sensing circuit having a second output, the current sensing circuit comprising a resistive divider coupled to the input of the transistor.

Methods and circuitry for driving a device

Modern FPGAs operate at a core voltage around 1V and therefore even small voltage fluctuations can lead to timing violations and logic errors. The Power Delivery Network (PDN) between a power supply and the FPGA core must be carefully designed to achieve a low output impedance over a broad range of frequencies. The present disclosure describes two techniques for characterization of the PDN: 1) to extract the DC resistance in the power delivery path, and 2) to identify the high impedance frequency band(s) in the PDN. An embedded impedance extraction tool is synthesized within the FPGA load, in coordination with a mixed-signal current-mode dc-dc converter. A self-calibrated Carry-Chain based ADC (CC-ADC) is used for high-speed sampling of the core voltage. By modifying the PDN based on the extracted results, the voltage operating range and reliability of a crossbar application may be greatly extended.

Characterization of power delivery network in field programmable gate arrays or digital integrated circuits

Disclosed are switched-mode DC-DC power converter modules, SMPC controllers, and distributed-control multiphase SMPC systems. The controller comprises: a reference clock; a synchronisation input configured to receive a first synchronisation signal; a synchronisation output configured to transmit a second synchronisation signal; a control unit configured to control the operation of the SMPC module with a phase determined by the reference clock signal or the first synchronisation signal; a delay line configured to generate the second synchronisation signal by adding a delay to the selected one of the first synchronisation signal and the reference clock signal; a fault detection terminal; a memory configured to store a datum corresponding to a number N of SMPCs in the system; and a delay calculation module configured to calculate the delay in dependence on the datum and the signal at the fault-detection terminal. Associated methods are also disclosed.

Distributed control of a multiphase power converter

A DC-DC converter selectively operates in at least a first burst mode having at least one first-mode charge cycle with a first-mode charging phase followed by a first-mode discharging phase or a second burst mode having at least one second-mode charge cycle with a second-mode charging phase followed by a second-mode discharging phase. A first-mode charging phase is terminated when an inductor current flowing through the inductance reaches a first-mode peak-current threshold, and a first-mode discharging phase is terminated when the inductor current reaches a first-mode valley-current threshold. A second-mode charging phase is terminated when the inductor current reaches a second-mode peak-current threshold, wherein the second-mode peak-current threshold is different from the first-mode peak-current threshold, and the second-mode discharging phase is terminated when the inductor current reaches a second-mode valley-current threshold, wherein the second-mode valley-current threshold is different from the first-mode valley-current threshold.

Charge-cycle control for burst-mode DC-DC converters

Embodiments provide forced-burst voltage regulation for burst mode direct-current-to-direct-current (DC-DC) converters in integrated circuits. The DC-DC converter generates an output voltage and operates in a burst mode to raise the output voltage to a threshold voltage. A controller is coupled to the DC-DC converter. In operation, the DC-DC converter is configured to perform the burst mode based upon a low-voltage detection for the output voltage. The DC-DC converter is further configured to perform the burst mode when a force-burst command is asserted by the controller to the DC-DC converter regardless of a state for the low-voltage detection. For one embodiment, the force-burst command is asserted as a burst control signal from the controller to the DC-DC converter to generate a long quiet period for sensitive actions. For another embodiment, the force-burst command is asserted using enable and refresh control signals to facilitate low-power operation.

Forced-burst voltage regulation for burst-mode DC-DC converters

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Olivier Trescases