Commissariat a L'energie Atomique Et Aux Energies Alternatives

Commissariat a L'energie Atomique

Stmicroelectronics (Crolles 2) Sas

Stmicroelectronics S.a.

Olivier Thomas

Maud Vinet

Bastien Giraud

Adam Makosiej

Thierry Poiroux

Olivier Rozeau

Philippe Coronel

Elisa Vianello

Jean-Philippe Noel

Stéphane Denorme

Michel Harrand

Perrine Batude

Marc Belleville

Costin Anghel

Claire Fenouillet-Béranger

Michael Collonge

Claire Fenouillet-Beranger

Gabriel Molas

Laurent Clavelier

Thomas Ernst

Olivier Weber

Jean-Michel Portal

Jean-Philippe Gros

Philippe Flatresse

Sébastien Brulais

Alexandre Valentian

Marie-Anne Jaud

Amara Amara

Prince Arnaud Ramahefa-Andry

Jerome Mazurier

Navneet Gupta

Nicolas Planes

Arnaud Pouydebasque

Vincent Liot

Jerome Paulet

Giorgio Palma

Santhosh Onkaraiah

Andrei Vladimirescu

Shashikanth Bobba

Herve Dang

Laurent Freytrich

Thomas-Medhi Benoist

Haithem Ayari

Yves Maneglia

The invention relates to field of connected sport and specifically a method for quantifying sporting activity implemented by a communication system including: a proximity beacon associated with sports equipment, measuring equipment and a communication node, the method including: (a) communicating between the measuring equipment and the beacon in order to recover a first data packet comprising an identifier relating to a sporting activity associated with the sports equipment; (b) transmitting, to the node, a second data packet comprising the identifier; (c) at the node, determining parameterisation data of the measuring equipment according to the identifier; (d) transmitting, to the measuring equipment, a third data packetcomprising said parameterisation data; and (e) at the parameterised measuring equipment, quantifying the sporting activity.

Method for quantifying a sporting activity

The invention relates to a resistive memory () including resistive elements, the resistance of each resistive element being capable of alternating between a high value in a first range of values and a low value in a second range of values smaller than the high value, the memory further comprising a device () for switching the resistance of at least one resistive element selected from among the resistive elements between the high and low values, the device including a first circuit capable of applying an increasing voltage across the selected resistive element while the selected resistive element is at the high value or at the low value, a second circuit capable of detecting the switching of the resistance of the selected resistive element, and a third circuit capable of interrupting the current flowing through the selected resistive element on detection of the switching.

Device and method for writing data to a resistive memory

The invention more particularly relates to a resistive memory cell comprising a first and a second metal electrodes and a solid electrolyte positioned between the first and the second metal electrodes, with the solid electrolyte comprising a commutation layer in contact with the first electrode and a dielectric layer, with said resistive memory cell being able to be electrically modified so as to switch from a first resistive state to a second resistive state (state LRS) wherein the resistance (R) of the memory cell is at least ten times smaller than the resistance (R) of the memory cell in the HRS state, in the LRS state the first electrode being so arranged as to supply metal ions intended to form at least a conductive filament through said commutation layer, with the cell being characterized in that, in the LRS state, the memory cell is conductive for a range of voltages between 0 Volts and 

Non-volatile resistive memory cell comprising metal electrodes and a solid electrolyte between the metal electrodes

Memory cell of the SRAM type, including storage transistors forming a memory point for storing a bit and a read port having at least one MOS transistor, a TFET transistor, a power terminal and a read bit line whereof a potential is designed to vary depending on the value of the stored bit, and such that:

Memory cell with read transistors of the TFET and MOSFET type to reduce leakage current

A content addressable memory having at least one CAM cell including first and second inverters cross-coupled between first and second storage nodes; a first transistor coupling the first storage node to a bitline, the first transistor being controlled by a first control signal; a second transistor coupling the second storage node to the bitline, the second transistor being controlled by a second control signal; and a control circuit adapted to perform a CAM read operation by pre-charging the bitline to a first voltage level, and then selectively activating either the first or second transistor based on a bit of input data.

Reconfigurable cam

A memory device includes a matrix of several columns of SRAM memory cells each including transistors forming a memory point, a read port and a write port, and such that the transistors of the read port and/or the P-type transistors include a second well with a conductivity type opposite that of a first well of the other transistors. The memory device also includes a polarization unit for the second wells, able to select and apply polarization potentials on the second wells, including a memory circuit of the polarization states of the second wells for each column or group of columns and a selection circuit applying a polarization potential on the second wells according to one of the values received as input, as a function of the stored polarization state associated with the column or group of columns.

Device with SRAM memory cells including means for polarizing wells of memory cell transistors

A non-volatile memory including a plurality of elementary cells, each cell including: a first programmable-resistance storage element connected between first and second nodes of the cell; a first access transistor coupling the second node to a third node of the cell; and a second access transistor coupling the second node to a fourth node of the cell.

Programmable-resistance non-volatile memory

The invention relates to a resistive memory including resistive elements, the resistance of each resistive element being capable of alternating between a high value and a low value, the memory further including a device for switching the resistance of at least one selected resistive element between the high and low values. The device includes a first circuit capable of circulating a first current through a first reference resistive component (R), a second circuit capable of circulating a second current proportional to the first current through the selected resistive element, a third circuit capable of detecting the switching of the resistance of the selected resistive element from the comparison of the voltage across the first reference resistive component with the voltage across the selected resistive element, and a fourth circuit capable of interrupting the second current on detection of the switching.

An integrated circuit on a semiconductor substrate has logic gates comprising FDSOI-type transistors made on said substrate, including at least one first transistor comprising a gate with a first work function, and including a transistor comprising a second work function, a memory including memory cells, each memory cell comprising FDSOI type transistors, including at least one third nMOS transistor with a gate presenting a third work function, the third transistor comprising a buried insulating layer and a ground plane at least one fourth pMOS transistor with a gate presenting said third work function, the fourth transistor comprising a buried insulating layer and a ground plane, the ground planes of the third and fourth transistors being made in a same well separating these ground planes from said substrate.

SOI integrated circuit comprising adjacent cells of different types

CMOS integrated circuits with very low consumption when idle, and notably the SRAM volatile memories, are provided. The inverters of the circuit are made up of an NMOS transistor and a PMOS transistor. A bias circuit applies a first rear bias voltage NBIAS to the wells of the NMOS transistors and a second rear bias voltage PBIAS to the wells of the PMOS transistors. The bias circuit comprises: a detection array made up of many inverters in parallel, having a common output supplying a logic signal whose value depends on the rear bias voltages applied to the array, a circuit for producing incrementation or decrementation pulses, controlled by the output of the detection array, and an integration circuit linked to the pulse-producing circuit, for producing and varying, progressively by increments in response to these pulses, a bias voltage PBIAS and a bias voltage NBIAS.

Circuit for reverse biasing inverters for reducing the power consumption of an SRAM memory

A manufacture includes an IC comprising a stacking of a semiconducting substrate, a buried insulating layer, and a semiconducting layer, a first electronic component formed in and/or on the semiconductor layer, a bias circuit to generate a first bias voltage, first and second via-type interconnections, to which the bias circuit applies a same bias voltage equal to the first bias voltage, a first insulation trench separating the first electronic component from the first and second interconnections, a first ground plane having a first type of doping, placed beneath the buried insulating layer plumb with the first electronic component, and extending beneath the first insulation trench and up into contact the first interconnection, and a first well having a second type of doping opposite that of the first type, plumb with the first ground plane, and extending beneath the first insulation trench and up into contact with the second interconnection.

Integrated circuit using FDSOI technology, with well sharing and means for biasing oppositely doped ground planes present in a same well

An integrated circuit includes a stack having a semiconductor substrate with a first type of dopant, an UTBOX type buried insulating layer, electronic components, formed in the substrate, ground planes disposed beneath the buried insulating layer so as to be respectively plumb with corresponding components, wells with the first type of dopant, the wells being respectively beneath corresponding ground planes, and a bias circuit enabling distinct voltages to be applied to the ground planes by the wells. The wells are separated from the substrate by a deep well with a second type of dopant. The wells are separated from each other by a separating structure, which is either a lateral well having a second type of dopant or a block of insulating material.

Self-contained integrated circuit including adjacent cells of different types

The invention relates to an integrated circuit including an active semiconducting layer separated from a semiconducting substrate layer by an embedded insulating material surface, including: first and second transistors () of a single type; first and second floorplans arranged vertically perpendicular to the first and second transistors; wherein the first transistor has a doping of the floorplan thereof, opposite that of the source thereof, and a first threshold voltage; the second transistor has a doping of the floorplan thereof, identical to that of the source thereof, and a second threshold voltage; the first threshold voltage is dependent on the potential difference applied between the source and the floorplan of the first transistor; and the second threshold voltage is dependent on the potential difference applied between the source and the floorplan of the second transistor.

Integrated circuit made out of SOI with transistors having distinct threshold voltages

A multi-level integrated circuit, having a superposition of a first stack and a second stack of layers, and including a first row of electronic devices produced in the first stack, extending parallel to a first direction and fitting into a first volume with a substantially parallelepiped rectangle shape and having edges perpendicular to the first direction and with dimension H; a second row of electronic devices produced in the second stack, extending parallel to the first direction and fitting into a second volume with a substantially parallelepiped rectangle shape and having edges perpendicular to the first direction and with dimension H&#x3c;H; and a plurality of electrical connection elements passing through the second stack of layers, each connection element fitting into a third volume arranged on the first volume and next to the second volume.

Multi-level integrated circuit, device and method for modeling multi-level integrated circuits

A support substrate comprises first and second counter-electrodes arranged in the same plane at the level of a surface of the support substrate. An electrically insulating area separates the first and second counter-electrodes. A semi-conducting area with first and second portions is separated from the support substrate by an electrically insulating material. The electrically insulating material is different from the material forming the support substrate. The first portion of the semi-conducting area is facing the first counter-electrode. The second portion of the semi-conducting area is facing the second counter-electrode.

Substrate provided with a semi-conducting area associated with two counter-electrodes and device comprising one such substrate

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Olivier Thomas