Nxp B.v.

St-ericsson Sa

St-ericsson (france) Sas

St-ericsson (grenoble) Sas

Olivier Tesson

Thomas Francois

Patrice Gamand

Magali Duplessis

Laure Rolland Du Roscoat

Mustafa Acar

Mathieu Perin

Christophe Cordier

Sidina Wane

Hamza Najjari

Hamza Nijjari

Pascal Talbot

Frédéric Francois Barbier

Konstantinos Giannakidis

An embodiment of passive phase shifter comprises a ground shield, a pair of ground walls electrically connected to the ground shield having a first height above the ground shield; and a signal line positioned between the ground walls and electrically isolated from the ground shield. The signal line may comprise an intermediate signal line separated a second height above the ground shield; a top signal line separated from the intermediate signal line at a third height above the ground shield and electrically connected to the intermediate signal line by one or more conductive vias; and a plurality of blocks positioned between and electrically isolated from the intermediate signal line and the top signal line.

Passive phase shifter for W band operation based on slow-wave tlines

A power combiner/splitter for multiple input multiple output (MIMO) applications and a method of making the same. A metallisation stack has a plurality of layers including patterned metal features forming first and second branched arrangements of the power combiner/splitter. Each branched arrangement includes a port located at one end of that branched arrangement, and a plurality of further ports. Each branched arrangement also includes a plurality of bifurcated branches extending between each end of that branched arrangement for dividing/combining a signal passing through that branched arrangement between the port and the plurality of further ports. The metallisation stack further includes a common ground plane that is shared by the first and second branched arrangements. At least some of the patterned metal features forming the first branched arrangement overlie at least some of the patterned metal features forming the second branched arrangement.

Power combiner/splitter for millimetre wave applications

An integrated circuit comprising a semiconductor substrate and a passive coupler located on the substrate. The coupler includes a solenoid. The coupler also includes a signal line passing through the solenoid. A method of making an integrated circuit. The method includes providing a semiconductor substrate and forming a passive coupler in a metallization stack on the substrate. Forming the passive coupler in the metallization stack on the substrate includes forming one or more windings of the solenoid using patterned metal features in a plurality of metal layers of the metallization stack. Forming the passive coupler in the metallization stack on the substrate also includes forming a signal line using one or more patterned metal features in one or more metal layers of the metallization stack. The signal line passes through the solenoid.

Integrated passive coupler and method

An integrated circuit for a packaged device is proposed. The circuit comprises: a circuit having first and second electromagnetic radiating elements fabricated on a die; a package substrate comprising an upper surface and a lower surface; and a grounding layer provided on the lower surface of the package substrate, the grounding layer being adapted to connect to a grounding plane of a printed circuit board. The die is mounted on the upper surface of the package substrate. The grounding layer comprises a void, at least a portion of the void being positioned so as to at least partially electromagnetically isolate the first electromagnetic radiating element from the second electromagnetic radiating element.

Integrated circuit

A semiconductor device comprising a switch and a method of making the same. The device, has a layout having one or more rectangular unit cells. Each unit cell includes a gate having a substantially cross-shaped part comprising four arms that divide the unit cell into quadrants; and a substantially loop-shaped part, wherein a center of the cross-shaped part is located inside the loop-shaped part, and wherein the loop-shaped part intersects each arm of the cross-shaped part to divide each quadrant into an inner region located inside the loop-shaped part; and an outer region located outside the loop-shaped part. Each unit cell also includes a substantially loop-shaped active region forming a source and drain of the switch. Each unit cell further includes a plurality of connection members extending over the gate, source and drain for providing electrical connections to the source and drain.

Semiconductor device comprising a switch

A semiconductor switch device and a method of making the same. The semiconductor switch device includes a field effect transistor located on a semiconductor substrate. The field effect transistor includes a plurality of gates. Each gate includes a gate electrode and gate dielectric arranged in a loop on a major surface of the substrate. The loops formed by the gates are arranged concentrically. Each gate has a source region located adjacent an inner edge or outer edge of the loop formed by that gate and a drain region located adjacent the other edge of said inner edge and said outer edge of the loop formed by that gate.

Semiconductor switch device

A semiconductor device comprising a switch and a method of making the same. The device has a layout that includes one or more rectangular unit cells. Each unit cell includes a gate that divides the unit cell into four corner regions. Each unit cell also includes a source comprising first and second source regions located in respective opposite corner regions of the unit cell. Each unit cell further includes a drain comprising first and second drain regions located in respective opposite corner regions of the unit cell. Each unit cell also includes a plurality of connection members extending over the gate, source and drain for providing electrical connections to the gate, source and drain.

A transformer comprising primary and secondary windings is disclosed. Each winding has first and second metal capping layers coupled together electrically in parallel by a metal connector passing through a substrate lying between the first and second metal capping layers.

Integrated transformer

A MOS varactor structure comprising a semiconductor body having a well region and a plurality of gate electrodes and a plurality of cathode electrodes arranged over the well region, wherein the gate electrodes comprise elongate pads, and the plurality of cathode contacts are connected by a cathode connection pattern, the cathode connection pattern comprising a plurality of arms, each of the plurality of arms arranged to extend over a part of a respective gate electrode pad.

Varactor structure

An integrated transformer comprising a primary coil and a secondary coil, the primary coil comprising a first subsection and a second subsection, the first subsection extending in a different plane to a plane in which the second subsection extends, the planes spaced from one another, the secondary coil comprising a first subsection and a second subsection, the first subsection extending in a different plane to a plane in which the second subsection extends, the planes spaced from one another, wherein the first subsection of the primary coil is stacked with the second subsection of the secondary coil and the second subsection of the primary coil is stacked with the first subsection of the secondary coil.

A Lange coupler comprises an unbroken peripheral ground conductor surrounding input, through, coupled and isolated conductor strips coupled to input, through, coupled and isolated ports of the Lange coupler respectively, wherein the peripheral ground conductor and input and through conductor strips are arranged on a first metal layer.

Lange coupler and fabrication method

A varactor comprises a substrate having sets of gate units each having parallel gate strips. The gate units are located such that the gate strips of neighboring gate units are oriented transverse to each other. An electrically conducting gate connection layer comprises gate connection units comprising parallel gate connection strips located over the gate strips, and a cathode connection frame around each of the gate connection units. A first electrically conductive anode layer comprises first layer anode strips located parallel to the gate connection strips and connected to alternate gate connection strips, and a first anode connection frame connected to the anode strips. A second electrically conductive anode layer comprises anode strips located parallel to the gate connection strips and connected to opposite alternate gate connection strips, and a second anode connection frame connected to the second layer anode strips.

Integrated circuit based varactor

A semiconductor package, comprises an encapsulant which contains a semiconductor substrate, the package lower side being mountable on a surface. The semiconductor substrate backside is in close proximity of the semiconductor package lower side for improved thermal conductivity to the surface. The active side of the semiconductor substrate, facing the upper side of the semiconductor package, has a plurality of die contacts. A plurality of electrically conductive interconnects are connected to the die contacts and extend to the lower side of the semiconductor package for connecting the die contacts to the surface.

Semiconductor package with improved thermal properties

The invention proposes a radio frequency circuit which comprises a transformer with a first primary circuit, a second primary circuit, and a secondary circuit, the secondary circuit comprising an integrated first inductor, this first inductor being positioned, on an axis orthogonal to a surface of the circuit, between an integrated second and third inductor respectively comprised in the first primary circuit and second primary circuit.

Growing community of inventors

Bretteville l'Orgueilleuse, France

Olivier Tesson