Texas Instruments Corporation

Olivier Schuepbach

Narendar M Shankar

Erdal Paksoy

Charles W Brokish

Steve Karouby

Mehdi-Laurent Akkar

Aymeric Stéphane Vial

An integrated circuit () includes an on-chip boot ROM () holding boot code, a non-volatile security identification element () having non-volatile information determining a less secure type or more secure type, and a processor (). The processor () is coupled to the on-chip boot ROM () and to the non-volatile security identification element () to selectively execute boot code depending on the non-volatile information of the non-volatile security identification element (). Other technology such as processors, methods of operation, processes of manufacture, wireless communications apparatus, and wireless handsets are also disclosed.

Less-secure processors, integrated circuits, wireless communications apparatus, methods for operation thereof, and methods for manufacturing thereof

Less-secure processors, integrated circuits, wireless communications apparatus, methods and processes of making

A system is provided that includes a processor and a random access memory (RAM) coupled to the processor. The RAM is divided into public RAM and secure RAM. The system also includes a system memory coupled to the processor, wherein the system memory stores RAM resize instructions that, when executed, enable the public RAM and the secure RAM to be dynamically resized. The system memory may also store save/restore secure RAM instructions that, when executed, perform a save operation that saves the secure RAM to non-volatile memory and a restore operation that restores the secure RAM from the non-volatile memory. The system memory may also store arbitration instructions that, when executed, enable a cryptographic hardware accelerator (HWA) to be shared by a secure application and a public application.

Methods and systems involving secure RAM

An integrated circuit () includes an on-chip boot ROM () holding boot code, a non-volatile security identification element () having non-volatile information determining a less secure type or more secure type, and a processor (). The processor () is coupled to the on-chip boot ROM () and to the non-volatile security identification element () to selectively execute boot code depending on the non-volatile information of the non-volatile security identification element(). Other technology such as processors, methods of operation, processes of manufacture, wireless communications apparatus, and wireless handsets are also disclosed.

A Reduced State Sequence Equalizer (RSSE) is implemented using a butterfly hardware accelerator () in the form of a butterfly to increase the efficiency of computing branch metrics () and the ACS (add, compare and select) function (). Multiple path metrics between a first state and a second state may be computed responsive to the received symbols and reference constellation symbols and determining a best scenario at the second state using said butterfly circuitry. The received symbols may be rotated by a predetermined angle for computation of all minimums of two cosets in an 8-PSK constellation.

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Antibes, France

Olivier Schuepbach