Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Commissariat a L'energie Atomique

Olivier Rozeau

Thierry Poiroux

Maud Vinet

Olivier Thomas

Laurent Grenouillet

Marie-Anne Jaud

Claire Fenouillet-Beranger

Alexei Tchelnokov

Bernard Previtali

Joris Lacord

Lina Kadura

Sebastien Martinie

Sébastien Martinie

Embodiments of the invention determine intrinsic parameters of stacked nanowires/nanosheets GAA MOSFETs comprising Nnanowires and/or nanosheets, each nanowire/nanosheet being surrounded in an oxide layer, the oxide layers being embedded in a common gate, wherein the method comprises the following steps:

Computer implemented method for determining intrinsic parameter in a stacked nanowires MOSFET

A photosensitive transistor device, on a semiconductor on insulator substrate, the photosensitive zone being formed in a substrate support layer and being arranged so that the concentration of photogenerated charges in the photosensitive zone can be increased towards a given zone facing the channel zone of the transistor.

Photosensitive detector with self-aligned 3D junction and gate

Photosensitive logic cell on a semiconductor-on-insulator substrate, possessing a P type transistor and an N type transistor fabricated on the front face of the substrate and whose respective threshold voltages can be modulated according to the quantity of photons received by a photosensitive zone provided opposite these transistors, the photosensitive zone possessing a photo-detection region whose arrangement is such that it favours illumination by the face of the photosensitive zone.

Front-illuminated photosensitive logic cell

Photosensitive logic inverter, in particular of the CMOS type, formed of a transistor of type P and of a transistor of type N of which the respective threshold voltages can be modulated according to the quantity of photons received by a photosensitive zone provided opposite these transistors.

CMOS photonic inverter

A method for making connection elements between two different levels of components in a 3D integrated circuit, including: forming a lateral insulating area supported on at least one given conducting area among several interconnection areas on a first level of components, the insulating area extending around a semiconducting layer on a second level in which at least one transistor can be formed; removing a first portion of the lateral insulating area so as to form at least one hole exposing said given conducting area; and depositing a conducting material in the hole so as to form a first electrical connection element between the second component and the given conducting area.

Manufacturing of self aligned interconnection elements for 3D integrated circuits

A computer implemented method for calculating a charge density qof a first gate of a double gate transistor comprising a thin body with a first and a second gate interface, the method including determining, using a physical processor, an initial estimate qof the charge density of the first gate; performing, using the physical processor, at least two basic corrections of the initial estimate based on a Taylor development of a function f(q) able to be nullified by a correct value of the charge density qof the first gate.

Computer implemented method for calculating a charge density at a gate interface of a double gate transistor

A method for making a microelectronic device with one or plural double-gate transistors, including: a) forming one or plural structures on a substrate including at least one first block configured to form a first gate of a double-gate transistor, and at least a second block configured to form the second gate of the double-gate, the first block and the second block being located on opposite sides of at least one semiconducting zone and separated from the semiconducting zone by a first gate dielectric zone and a second gate dielectric zone respectively; and b) doping at least one or plural semiconducting zones in the second block of at least one given structure among the structures, using at least a first implantation selective relative to the first block, the implantation being done on a first side of the given structure, the part of the structure on the other side of the normal to the principal plane of the substrate passing through the semiconducting zone not being implanted.

Method for making asymmetric double-gate transistors

A method for fabricating a microelectronic device with one or several asymmetric and symmetric double-gate transistors on the same substrate.

Method for fabricating asymmetric double-gate transistors by which asymmetric and symmetric double-gate transistors can be made on the same substrate

A method for fabricating a microelectronic device with one or plural double-gate transistors, including: a) forming one or plural structures on a substrate including at least a first block configured to form a first gate of a double-gate transistor, and at least a second block configured to form the second gate of said double-gate, the first block and the second block being located on opposite sides of at least one semiconducting zone and separated from the semiconducting zone by a first gate dielectric zone and a second gate dielectric zone respectively, and b) doping at least one or plural semiconducting zones in the second block of at least one given structure among the structures, using at least one implantation selective relative to the first block, the second block being covered by a hard mask, a critical dimension of the hard mask being larger than the critical dimension of the second block.

Method for making asymmetric double-gate transistors by which asymmetric and symmetric double-gate transistors can be made on the same substrate

A method for fabricating a microelectronic device with one or plural asymmetric double-gate transistors, including: a) forming one or plural structures on a substrate including at least a first semiconducting block configured to form a first gate of a double-gate transistor, and at least a second semiconducting block configured to form a second gate of the double-gate transistor, the first block and the second block being located on opposite sides of at least one semiconducting zone and separated from the semiconducting zone by a first gate dielectric zone and a second gate dielectric zone respectively, and b) doping at least one or plural semiconducting zones in the second block of at least one given structure among the structures, using at least one implantation selective relative to the first block.

Growing community of inventors

Moirans, France

Olivier Rozeau