Nxp Usa, Inc.

Freescale Semiconductor,inc.

Olivier Lembeye

Jeffrey Kevin Jones

Enver Krvavac

Kevin Kim

Cedric Cassan

Pascal Peyrot

Joseph Gerard Schultz

Damon G Holmes

Ning Zhu

David Cobb Burdeaux

Daniel J Lamey

Jeffrey Spencer Roberts

Igor Blednov

Xavier Hue

Sai Sunil Mangaonkar

Anthony Lamy

Xavier Moronval

Embodiments of a device and method are disclosed. In an embodiment, a Doherty amplifier module includes a first amplifier die with a first output terminal, a second amplifier die with a second output terminal, and a wideband impedance inverter circuit electrically coupled between the first and second output terminals. The wideband impedance inverter circuit includes a network of capacitors, the network of capacitors including at least a series capacitor having a positive capacitance, a first shunt circuit having a first negative capacitance, and a second shunt circuit having a second negative capacitance.

Doherty amplifier module with compact wideband impedance inverter

Embodiments of RF amplifiers and packaged RF amplifier devices each include an amplification path with a transistor die, and an output-side impedance matching circuit having a T-match circuit topology. The output-side impedance matching circuit includes a first inductive element (e.g., first wirebonds) connected between the transistor output terminal and a quasi RF cold point node, a second inductive element (e.g., second wirebonds) connected between the quasi RF cold point node and an output of the amplification path, and a first capacitance connected between the quasi RF cold point node and a ground reference node. The RF amplifiers and devices also include a baseband termination circuit connected to the quasi RF cold point node, which includes an envelope resistor, an envelope inductor, and an envelope capacitor coupled in series between the quasi RF cold point node and the ground reference node.

Broadband power transistor devices and amplifiers with output T-match and harmonic termination circuits and methods of manufacture thereof

Aspects of the subject disclosure may include a power splitter. The power splitter can include a first splitter branch having a first amplifier with passive components, a second splitter branch having a second amplifier with passive components. The first splitter branch is substantially electrically isolated from the second splitter branch by configuring the first and second splitter branches to have similar phase delays. Outputs of the power splitter can be electrically coupled to the multi-stage amplifier. The power splitter can be manufactured on a single semiconductor die or integrally formed on the same semiconductor die with other circuits such as the multi-stage amplifier. Other embodiments are disclosed.

Integrally-formed splitter for multiple-path power amplifiers and methods of manufacture thereof

A multiple-stage amplifier includes a driver stage die and a final stage die. The driver stage die includes a first type of semiconductor substrate (e.g., a silicon substrate), a first transistor, and an integrated portion of an interstage impedance matching circuit. A control terminal of the first transistor is electrically coupled to an RF signal input terminal of the driver stage die, and the integrated portion of the interstage impedance matching circuit is electrically coupled between a current-carrying terminal of the first transistor and an RF signal output terminal of the driver stage die. The second die includes a III-V semiconductor substrate (e.g., a GaN substrate) and a second transistor. A connection, which is a non-integrated portion of the interstage impedance matching circuit, is electrically coupled between the RF signal output terminal of the driver stage die and an RF signal input terminal of the final stage die.

Multiple-stage power amplifiers implemented with multiple semiconductor technologies

Embodiments of an RF amplifier include a transistor with a control terminal and first and second current carrying terminals, and a shunt circuit coupled between the first current carrying terminal and a ground reference node. The shunt circuit is an output pre-match impedance conditioning shunt circuit, which includes a first shunt inductance, a second shunt inductance, and a shunt capacitor coupled in series. The first shunt inductance comprises a plurality of bondwires coupled between the first current carrying terminal and the second shunt inductance, and the second shunt inductance comprises an integrated inductor coupled between the first shunt inductance and a first terminal of the shunt capacitor. The shunt capacitor is configured to provide capacitive harmonic control of an output of the transistor.

RF power transistors with impedance matching circuits, and methods of manufacture thereof

A system and method for a packaged device with harmonic control are presented. In one embodiment, a device includes a substrate and a transistor die coupled to the substrate. The transistor die includes a plurality of transistor cells. Each transistor cell in the plurality of transistor cells includes a control (e.g., gate) terminal. The device includes a second die coupled to the substrate. The second die includes a plurality of individual shunt capacitors coupled between the control terminals of the plurality of transistor cells and a ground reference node. The capacitance values of at least two of the shunt capacitors are significantly different.

Power transistor with harmonic control

In a system comprising a plurality of gain elements configured in parallel to one another, a harmonically tuned filter provides an isolation circuit to prevent odd-mode differential oscillations. A harmonically tuned filter comprises resistors, inductors, and capacitors (RLC) to selectively allow one or more specific harmonics to pass through the isolation circuit to suppress the odd-mode oscillation. Direct current (DC) and other non-harmonically-related frequencies do not pass through the isolation circuit. Since the resistor is used to dissipate specifically the energy of the harmonic frequencies causing the odd-mode oscillation, the current density through the resistor is much lower than the current density of a typical odd-mode resistor without a harmonically tuned filter.

Frequency selective isolation circuit and method for suppressing parametric oscillation

An RF amplifier includes a harmonic filter with a plurality of shunt filter legs. The harmonic filter provides a suppressing frequency range for a harmonic frequency of a carrier frequency in a range of carrier frequencies. Each of the shunt filter legs includes capacitor, inductor, and a node coupled between the capacitor and inductor. Each node of the shunt filter leg is coupled to at least one other node of another shunt filter leg of the filter with a resistive element. The harmonic filter includes a first shunt filter leg that has a resonant frequency between the center frequency and (1/1.220) times the center frequency and a second shunt filter leg that has a resonant frequency between the center frequency and 1.220 times the center frequency.

Harmonic filter for RF amplifier

A packaged RF amplifier device includes a transistor and an output circuit. The transistor includes a control terminal and first and second current carrying terminals. The output circuit is coupled between the first current carrying terminal and an output lead. The output circuit includes first and second inductive elements coupled in series. The first inductive element, which may be a first bondwire array or an integrated inductance, is coupled between the first current carrying terminal and a node. The second inductive element, which includes a second bondwire array, is coupled between the node and the output lead. The device also includes a shunt circuit with a shunt capacitor and a third bondwire array coupled between the first current carrying terminal and the shunt capacitor. The first and second inductive elements and the third bondwire array are configured to have a desired mutual inductance.

Output impedance matching circuit for RF amplifier devices, and methods of manufacture thereof

An electrostatic discharge (ESD) protection circuit () is coupled across input-output (I/O) pads () and common terminals () of a circuit core () to protect it from ESD events. The circuit () comprises, a unidirectional ESD clamp () and two or more floating diodes () arranged in parallel opposed configuration in series with the ESD clamp (), the combination coupled between the I/O pads () and the reference terminals (). In a preferred arrangement, the two strings of opposed parallel coupled diodes () are used with different numbers of diodes in each string. These diodes () operate in forward conduction (), so the energy dissipated therein during an ESD event is much reduced compared to a reverse biased diode and they can have smaller area. Signal clipping at the I/O pad () is reduced, less power is dissipated and less chip area is utilized.

Methods of forming electronic elements with ESD protection

An electrostatic discharge (ESD) protection circuit () is coupled across input-output (I/O) pads () and common terminals () of a core circuit () to protect it from ESD events. The circuit () comprises, a unidirectional ESD clamp () and two or more floating diodes () arranged in parallel opposed configuration in series with the ESD clamp (), the combination coupled between the I/O pads () and the reference terminals (). In a preferred arrangement, the two strings of opposed parallel coupled diodes () are used with different numbers of diodes in each string. These diodes () operate in forward conduction (), so the energy dissipated therein during an ESD event is much reduced compared to a reverse biased diode and they can have smaller area. Signal clipping at the I/O pad () is reduced, less power is dissipated and less chip area is utilized.

ESD protection using isolated diodes

A protection circuit apparatus comprises an electrostatic discharge circuit coupled to an isolation filter. The isolation filter comprises an inductor coupled to a ground-coupled capacitor, the inductor and the capacitor being coupled to the electrostatic discharge circuit. The inductor is also coupled to an electrostatic discharge sensitive device to be protected from an electrostatic discharge event.

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Saint Lys, France

Olivier Lembeye