Infineon Technologies Austria Ag

Olivier Guillemant

David Laforet

Li Juin Yip

Cedric Ouvrard

Cesar Augusto Braz

Giuseppe Bernacchia

Gerhard Noebauer

A power semiconductor device includes a semiconductor substrate having a first side. A plurality of active transistor cells is formed in an active area of the semiconductor substrate. Each of the plurality of active transistor cells includes a spicular trench which extends from the first side into the semiconductor substrate and has a field electrode. A gate electrode structure has a plurality of intersecting gate trenches running between the spicular trenches. The intersecting gate trenches form gate crossing regions of different shape when seen in a plan projection onto the first side of the power semiconductor device.

Power semiconductor device having different gate crossings, and method for manufacturing thereof

A vertical semiconductor field-effect transistor includes a semiconductor body having a front side, and a field electrode trench extending from the front side into the semiconductor body. The field electrode trench includes a field electrode and a field dielectric arranged between the field electrode and the semiconductor body. The vertical semiconductor field-effect transistor further includes a gate electrode trench arranged next to the field electrode trench, extending from the front side into the semiconductor body, and having two electrodes which are separated from each other and the semiconductor body. A front side metallization is arranged on the front side and in contact with the field electrode and at most one of the two electrodes.

Semiconductor transistor and method for forming the semiconductor transistor

A power converter with an isolated topology may include a power transistor, a sense transistor, and a read-out circuit. The sense transistor may be arranged in a current mirror configuration with the power transistor such that the gate terminal of the sense transistor is coupled to the gate terminal of the power transistor and the first drain/source terminal of the sense transistor is coupled to the first drain/source terminal of the power transistor. The read-out circuit may be coupled to the second drain/source terminal of the power transistor and the second drain source/terminal of the sense transistor. The read-out circuit may be arranged to cause a voltage at the second drain/source terminal of the sense transistor to be substantially the same as a voltage at the second drain/source terminal of the power transistor.

Growing community of inventors

Villach, Austria

Olivier Guillemant