Stmicroelectronics S.a.

Stmicroelectronics (rousset) Sas

Stmicroelectronics (grenoble 2) Sas

Olivier Ferrand

Bruno Gailhard

Ludovic Ruat

Dragos Davidescu

Emmanuel Ardichvili

Jean-Michel Gril-Maffre

Sandrine Lendre

Daniel Olson

Christophe Pinatel

Serge Mazer

Anis Ben Said

A system includes an electronic module and an integrated circuit outside the electronic module. The integrated circuit is configured to generate a digital timing signal that emulates a first synchronization signal internal to the module and not available outside the module and to generate trigger signals based on the digital timing signal. A controller is configured to independently and autonomously perform control operations of the electronic module at times triggered by the trigger signals.

Method of producing triggering signals for a control of a multimedia interface

Method of producing triggering signals for control of a multimedia interface

An image processing electronic device includes a pipeline configured to process frames of image data; an internal memory coupled to the pipeline, wherein a set of descriptors arranged according to an order is stored in the internal memory, each descriptor of the set of descriptors is associated with a corresponding function to be activated by the pipeline on at least one frame of image data; a controller configured to read each descriptor of the set of descriptors sequentially and cyclically according to the order at a rate of at least one descriptor per one frame of image data and store information corresponding to each read descriptor, wherein the pipeline is configured to activate on each frame of image data, the function associated with each read descriptor based on the stored information.

Electronic image processing device

A method can be used monitoring a task for an electronic module. The method includes waiting for performance of the task, timing the wait, the timing being regulated by a clock signal and generating an alert signal when the timing of the wait has exceeded a reference value. The device can be part of a multimedia interface (e.g., a display) electronic module and the task a graphical task (e.g., an image refresh).

Method of monitoring a task for an electronic module

In accordance with an embodiment, a method for managing access to a bus shared by interfaces includes: when to the bus is granted to one of the interfaces, triggering a counting having a minimum counting period; and when at least one access request to the bus emanating from at least one other of the interfaces is received during the minimum counting period, releasing the access granted to the one of the interfaces, and creating an arbitration point at an end of the minimum counting period.

Method for managing access to a shared bus and corresponding electronic device

An embodiment system includes a first processor configured to process a suite of instructions and a second processor configured to process a subset of the suite of instructions. The system further includes a power management circuit configured to select the first processor or the second processor as a selected processor, the power management circuit being further configured to activate the selected processor or place the selected processor on standby. The system also includes a first peripheral device configured to generate a first interrupt signal, a switch configured to direct the first interrupt signal to the selected processor, and a first memory configured to store a first interrupt routine associated with the first interrupt signal, the selected processor being configured to execute the first interrupt routine in response to the first interrupt signal.

System and method for processing interrupts by processors of a microcontroller in a low-power mode

A microprocessor includes a computation unit having logic units for executing operations associated with determined instructions of a microprocessor instruction set and a control unit for interpreting the instructions and for controlling the logic units accordingly. An internal timer of the microprocessor is activated by the control unit in response to the execution of a dedicated standby instruction of the microprocessor instruction set. Responsive thereto, a timeout signal is delivered to the control unit so as to place the microprocessor in a standby state during a determined timeout period.

Device and method for managing a standby state of a microprocessor

A smart card reader includes a housing for receiving a smart card, a microprocessor, and a connector for connecting the microprocessor to the received smart card for establishing communications therebetween. A voltage source provides a power supply voltage to the microprocessor based upon the smart card being received in the housing. The smart card reader further includes a first switch interposed between the voltage source and a power supply terminal of the microprocessor. The first switch is closed when the received smart card is at an end of travel in the housing so that the power supply voltage is provided to the microprocessor, and is opened when the received smart card is no longer at the end of travel in the housing so that the power supply voltage is not provided to the microprocessor.

Card reader comprising an energy-saving system

A temperature-compensated current source includes a first arm fixing a reference voltage, a second arm fixing a reference current, and a third arm providing an output current obtained by copying the reference current in a first current mirror. A second current mirror copies, in the voltage reference arm, the reference current while a voltage copying circuit copies the reference voltage at a node of the second arm connected to ground by a first resistor series-connected with n parallel-connected diodes. A second resistor is parallel-connected with the assembly formed by the first resistor series-connected with the n parallel-connected diodes.

Temperature-compensated current source

A generator includes an oscillator for producing a clock signal from an N-bit control number. The oscillator includes a first group of cells, with each cell including at least one series connected inverter. A first selection circuit selects a variable number of the cells as a function of the most significant bits of the control number. The oscillator also includes a second group of cells, with each cell including at least one series connected inverter. A second selection circuit selects one of the cells as a function of the least significant bits of the control number. The selected cells of the first and second groups of cells are series connected to form a chain of inverters.

Precise digital generator producing clock signals

An integrated circuit includes a generator for providing a clock signal from a reference signal. The generator, which is of the phase-locked loop type, includes a frequency divider and a phase comparator connected together. A reset circuit is connected to the frequency divider and to the phase comparator for providing a reset signal thereto at each leading edge of the reference signal for synchronizing a low-frequency signal with the reference signal.

Generator for the production of clock signals

A generator producing a clock signal whose frequency depends on a control voltage includes a comparator for comparing a period of the clock signal with a desired period, and for providing at least one first control signal based upon the comparison. The generator includes a sampler circuit for sampling the first control signal, and for producing a first sampled control signal. The generator also includes a voltage generator for providing the variable control voltage as a function of the first sampled control signal.

Small-sized analog generator producing clock signals

A generator includes an oscillator for producing a clock signal from N logic signals representing an N-bit control number, with N being an integer greater than 1. The oscillator has N&plus;1 components. The N most significant components are each assigned a place value i ranging from 1 to N, and a least significant component provides the clock signal. At least one component with a place value i greater than 1 includes first and second arms. The first arm includes a cell and a first switch connected in series, and the second arm includes 1&plus;2 cells and a second switch connected in series. Each cell includes an odd number of inverters.

Small-sized digital generator producing clock signals

The invention relates to a digital timer ( ) comprising a binary counter ( ) driven by a counting clock signal (Hc), the counter ( ) presenting a stabilization time after each counting pulse, and means for delivering a detection signal (DS ) with a predetermined value when a counting order (N) is reached by the counter. According to the invention, the timer comprises wired logic means ( ) arranged for detecting, at the output of the counter, a counting value (N&minus;1) which is immediately before the counting order (N) in relation to the counting direction, and delivering an intermediate signal (DS ) with a predetermined value, as well means ( ) for sampling the intermediate signal (DS ) at a moment when the counter receives the next counting pulse.

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Puyloubier, France

Olivier Ferrand