Synopsys, Inc.

Olivier Coudert

Solaiman Rahim

Alexander John Wakefield

Gagan Vishal Jain

Johnson Adaikalasamy

Ritesh Mittal

Mikhail Bershteyn

Florent Sébastien Marc Emmanuel Claude Duru

Florent Duru

Gilles Pierre Rémond

Songra Pan

Tien-Chien Lee

Suman Nandan

Francois Peneloux

Krishanu Debnath

Disclosed is a configuration to compute weakly connected components (WCCs) in a parallel, scalable and deterministic manner. The configuration receives an undirected original graph having vertices and edges. An undefined value is assigned to all the vertices of the graph. Thereafter, each vertex is visited and assigned a WCCID (index to identify a WCC). The visitation of vertices may determine whether there are one or more thread collisions. A collision is when two threads attempt to identify the same WCC. From these collisions a new graph may be generated, a collision graph, on which the same algorithm is iterated to compute WCCs of that collision graph. The process is iterated until no further collisions are determined. In a post process, the configuration merges the WCCIDs of the collision graphs to produce the WCCIDs of the original graph.

Computation of weakly connected components in a parallel, scalable and deterministic manner

A system obtains deterministic results of netlist transformation in a multi-processor parallel computing system. The system receives a netlist. The system determines a set of components representing components with assigned identifiers. The system determines identifiers for remaining components. The system visits a component of the remaining components of the netlist in a topological order starting from the set of components. The system assigns a new identifier to the visited component. The new identifier is generated based on properties of the visited component and a connection of the visited component with at least one component of the set of components. Once the component is assigned an identifier, the system adds the component to the set of components. The system repeats these steps to assign an identifier to remaining components that are not included in the set.

Deterministic netlist transformations in a multi-processor parallel computing system

Described is a configuration to remove false paths from an emulation netlist in a chip design under test (DUT). The configuration identifies, in an original netlist, an original subgraph of original logic gates, a subset of inputs (TI), and a subset of outputs (TO). The configuration generates a replicated subgraph of the original subgraph, the replicated subgraph having replicated logic gates corresponding to the original logic gates. The configuration connects the TI with a first replicated logic gate to a constant propagation source and remaining inputs of the replicated logic gates with corresponding original logic gates in the original netlist. The configuration disconnects, in the original netlist, output loads of TO, and connects the output loads of TO with a corresponding equivalent TO in the replicated subgraph. The configuration deletes, in the original netlist, original logic gates unconnected with an output load for TO in the original netlist.

Non-functional loopback-paths removal from IO-pads using logic replication

Disclosed herein are system, method, and computer program product embodiments for partitioning large circuits into balanced portions for independent simulation. Embodiments include generating a reduced graph by removing a plurality of startpoint vertices from a graph corresponding to a circuit. A plurality of small weakly connected components (SWCCs) and a plurality of large weakly connected components (LWCCs) corresponding to the reduced graph are computed. A first plurality of balanced subgraphs based on the plurality of SWCCs, and a second plurality of balanced subgraphs based on the plurality of LWCCs, where each balanced subgraph of the first and second plurality of balanced subgraphs can be simulated using a simulator with a processing capacity less than or equal to a memory limit are generated. The first and the second plurality of balanced subgraphs are simulated.

Partitioning a circuit for distributed balanced independent simulation jobs with upper-bounded memory

A process is disclosed to identify the minimal set of sequential and combinational signals needed to fully reconstruct the combinational layout after emulation is complete. A minimal subset of sequential and combinational elements is output from the emulator to maximize the emulator speed and limit the utilization of emulator resources, e.g., FPGA resources. An efficient reconstruction of combinational waveforms or SAIF data is performed using a parallel computing grid.

Waveform based reconstruction for emulation

A circuit hardware emulation module is configured to identify oscillating subgraphs of an emulated graph, or to identify state-holding subgraphs of an emulated graph. The emulation module identifies one or more loops within an emulated circuit; generates an acyclic emulation of at least a portion of the emulated circuit, wherein the acyclic emulation is characterized by one or more loop breakers; generates a loop detector emulation of a hardware-based loop detector circuit based at least in part on a quantity of loop breakers n characterizing the acyclic emulation, wherein the loop detector emulation comprises at least one of an oscillation detector or a state-holding detector; and executes the loop detector emulation for a plurality of input values for the emulated circuit to generate an output indicating at least one of an oscillation status or a state-holding status of the emulated circuit.

Hardware simulation systems and methods for identifying state-holding loops and oscillating loops

An example is a method. A design of an integrated circuit is loaded onto an emulation system and is emulated by the emulation system. A sequence of frames is captured, by the emulation system, from the emulation. The sequence of frames includes frame intervals, and each frame interval includes a full frame and a delta primary frame subsequent to the full frame. The full frame is captured at a respective sample time, and the full frame includes signals of the design or a change of the signals relative to a respective sample time of the full frame of a previous frame interval. The delta primary frame is captured at a respective sample time, and the delta primary frame includes a change of a subset of the signals relative to a respective sample time of a previous frame of the respective frame interval. The sequence of frames is stored to memory.

Growing community of inventors

Mountain View, CA, United States of America

Olivier Coudert