Infineon Technologies North America Corp.

Infineon Technologies Ag

Other

International Business Machines Corporation

Oliver Weinfurtner

Matthew R Wordeman

Louis L C Hsu

Louis L Hsu

Wayne Frederick Ellis

Gerhard Mueller

Brian L Ji

Yujon Li

Apparatus is used to dynamically control the power output of generators of a generator system on a chip to load circuits on the chip. A power bus is directed along at least one &ldquo;spine&rdquo; section on the chip which may intersect with at least one &ldquo;arm&rdquo; section on the chip for supplying power from the generators, which are coupled to the power bus in the &ldquo;spine&rdquo; section thereof, to circuits on the chip. The power bus has a feedback lead from each end which is remote from the generators for providing a continuous measurement of a voltage drop occurring at each remote end. At least one detector circuit is located at a predetermined point adjacent the generators of the chip for comparing a voltage from the generators measured at the predetermined point with the concurrent voltage drop measured at an associated remote end. In response to such comparison, the at least one detector circuit generates control signals for transmission to the generators for altering a generated voltage to maintain a predetermined power level on the power bus in response to load changes caused by the circuits on the chip.

Generator scheme and circuit for overcoming resistive voltage drop on power supply circuits on chips

A circuit for storing a bit of data is provided, where the circuit includes a first fuse having a first end and a second end and a second fuse having a third end and a fourth end. The first end of the first fuse is connected to a logic 0 input and its second end is connected to a common output. The third end of the second fuse is connected to a logic 1 input and the fourth end is connected to the common output. To store the bit of data, one of the first and second fuses is selectively blown. Hence, two fuses can be used to store a bit of information.

Memory cell

A charge pump generator system and method is provided in which one or more charge pumps are operated at multiple charging rates depending upon the level reached by a voltage supply. The system includes a limiter which provides a control signal based upon the level of the voltage supply. The control signal selects the frequency of a multiple frequency oscillator coupled thereto. The selected frequency determines the charge transfer rate of a charge pump used to maintain the voltage supply.

Charge pump system having multiple charging rates and corresponding method

A voltage pump system for programming fuses on a semiconductor chip, in accordance with the present invention, includes a first pump system employing a supply voltage of the semiconductor chip as an input. The first pump system supplies an output voltage higher than the supply voltage on a first output line without raising the supply voltage of the semiconductor chip. A second pump system includes an input connected to the first output. The second pump system supplies an output voltage sufficient for programming electrical fuses on the semiconductor chip.

High voltage pump system for programming fuses

A charge pump generator system and method is provided which more precisely maintains the level of an internally generated voltage supply by operating some or all of the available charge pumps depending upon the voltage level reached by the voltage supply. When the voltage supply is far from its target level, a first group and a second group of charge pumps are operated. The first group may preferably have a faster pumping rate or a greater number of charge pumps than the second group. When the voltage supply exceeds a first predetermined level, the first group of charge pumps is switched off while the second group remains on, such that the rate of charge transfer slows. The second group continues operating until a second, e.g. target, voltage level is exceeded. The slower rate of charge transfer then effective reduces overshoot, ringing and noise coupled onto the voltage supply line. Preferably, at least one charge pump operates in both standby and active modes, thereby reducing chip area.

Charge pump system having multiple independently activated charge pumps and corresponding method

In a controller for controlling a generator system on a memory chip, the controller operates as a state machine in accordance with a state diagram including a plurality of X states. A state storage device is responsive to input signals indicating a change in the state diagram from a current state to a next state for generating a revised plurality of X state output signals comprising a true State signal and a complementary true State signal for the next state of the plurality of X states. An output arrangement is responsive to the true State signal and the complementary true State signal in the revised plurality of X state output signals from the state storage device for generating separate predetermined ones of M output signals associated with said next state for controlling the generator system while providing substantially zero current consumption when the state diagram reaches a final state of the plurality of X states.

Method and apparatus for a flexible controller including an improved output arrangement for a DRAM generator system

Improved transistor array device performance is obtained by use of bias voltage regulation which tracks with a fraction of a monitor transistor threshold voltage. The circuitry and methods are especially useful for improving the performance of transistor array devices such as DRAM and embedded DRAM. These benefits are obtained especially when at least two bias voltages normally supplied to the array are regulated by tracking with a fraction of an actual threshold voltage of at least one monitor transistor. Performance improvements include improved reliability, wider operational bias conditions, reduced power consumption and (in the case of memory cells) improved retention time.

Multi-generator, partial array Vt tracking system to improve array retention time

In a controller for controlling a generator system on a memory chip, the controller operates as a state machine in accordance with a state diagram including a plurality of X states. An evaluation arrangement evaluates a combination of only a predetermined one of a plurality of N input signals from remote devices, and only a predetermined one of a plurality of X state signals indicating a current state in the state diagram at any instant of time. The controller generates a plurality of Y output signals having a predetermined logical value that indicates that a change from one state to a next state in the state diagram is to be made when the predetermined one of both the plurality of N input signals and the plurality of X state signals comprise a predetermined logical value. A state storage device is responsive to the predetermined one of a plurality of Y output signals having a predetermined logical value, and generates a revised plurality of X state output signals for transmission back to the evaluation arrangement indicating a change in the state diagram from a current state to a next state of the plurality of X states. An output arrangement is responsive to the revised plurality of X state output signals for generating separate predetermined ones of M output signals to remote devices associated with said next state for controlling the generator system.

Method and apparatus for a flexible controller for a DRAM generator system

In a flexible programmable controller for controlling a generator system on a memory chip, the controller operates as a state machine in accordance with a state diagram including a plurality of X states. A state storage device is responsive to input signals indicating a Reset state or a change in the state diagram from a current state to a next state for generating a Reset and an associated complementary Set signal or a revised plurality of X state output signals comprising a true State signal and a complementary true State signal for the next state of the plurality of X states. An output arrangement is responsive to the Reset and complementary Set signals or the true State signal and the complementary true State signal in the revised plurality of X state output signals from the state storage device for generating separate predetermined ones of M output signals associated with said Reset or next state for controlling the generator system.

Method and apparatus for an improved reset and power-on arrangement for

A plurality of voltage generating circuits forming a voltage generator system on a chip are controlled by a centralized voltage generator control arrangement. The voltage generator control arrangement includes a controller with a state machine (52) that receives control signals from various devices on the chip as, for example, a clock generator, voltage detectors, bondpads, testpads, fuses, and predetermined registers. From the received signals, the controller generates control signals to the plurality of generating circuits of the voltage generator system and other circuits on the chip in accordance with a predetermined program sequence for each phase of operation required by the generating circuits to provide the necessary stable voltages to circuits on the chip.

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Wappingers Falls, NY, United States of America

Oliver Weinfurtner