Infineon Technologies Ag

Infineon Technologies Austria Ag

Eupec Europaeische Gesellschaft Fuer Leistungshalbleiter Mbh & Co. Kg

Oliver Schilling

Paul Frank

Frank Wagner

Sven Schmidbauer

Reinhold Spanke

Thomas Heinelt

Frank Dieter Pfirsch

Ulrich Wilke

Thomas Nuebel

Joachim Seifert

Martin Woelz

Thomas Passe

Roman Immel

Altan Toprak

Lars Boewer

A semiconductor device includes a semiconductor die including a first side and an opposing second side, a first metallization layer arranged on the first side, a Ni including layer arranged on the second side, wherein the Ni including layer further includes one or more of Si, Cr and Ti, and a SnSb layer arranged on the Ni comprising layer, wherein an amount of Sb in the SnSb layer is in the range of 2 wt % to 30 wt %.

Semiconductor device with a nickel comprising layer and method for fabricating the same

A semiconductor device includes a semiconductor wafer or a single semiconductor chip or die, and a layer stack. The layer stack comprises a first layer comprising NiSi, and a second layer comprising NiV, wherein the second layer is arranged between the first layer and the semiconductor wafer or single semiconductor chip or die.

Semiconductor device having a layer stack, semiconductor arrangement and method for producing the same

Semiconductor device, semiconductor arrangement and method for producing the same

A power semiconductor device includes a semiconductor body. The semiconductor body includes a body region of a first conductivity type for forming therein a conductive channel of a second conductivity type; a gate electrode arranged next to the body region; and a floating electrode arranged between the gate electrode and the body region.

Short circuit limiting in power semiconductor devices

The power semiconductor module () has a heat-conducting base plate () on which at least three substrates () are placed, each substrate supporting at least one power semiconductor component () that gives off heat generated during operation. In order to optimize a power semiconductor module of this type with regard to mechanical load and heat dissipation, the substrates () are placed on the base plate () while being arranged in a single row (), and pressing devices (), which are situated close to the substrate, are provided on both longitudinal sides () of the base plate () while being arranged parallel to the row (). The base plate can be pressed against a cooling surface by the pressing devices.

Power semiconductor module having a thermally conductive base plate on which at least four substrates are arranged in at least one single row

A power module has several circuit units () that are electrically connected in parallel and are provided with terminal contacts (') which are electrically and mechanically interconnected via at least one current-conducting saddle (). In order to create a power module which is easy to produce and in which the current-conducting saddle () requires little space, the saddle () is embodied in several parts while encompassing a terminal element () that can be connected in a fixed manner to a terminal contact () of a circuit unit () independently of a connecting element () of the saddle (). The connecting element () of the saddle () extends on a plane that is spaced apart from the circuit unit () while being electrically connected to the terminal element ().

Power module

A power semiconductor module having a carrier plate, on which at least four substrates are arranged, and having a first and a second busbar having two conductive plates is disclosed. The conductive plates are arranged such that they are at a distance from one another and are insulated from one another, for respectively carrying a lower and an upper electrical potential, said busbars each being fitted with outer connecting lugs which lead away from the substrates and inner connecting lugs on the substrate side. Symmetrization of the current during dynamic commutation operations is achieved by correctly selecting the order of the outer connecting lugs of the respective first busbar for a lower potential and of the second busbar for an upper potential in accordance with the order of the inner connecting points of the parallel-connected half-bridge circuits and also of the inner connecting lugs of the first busbar and of the second busbar.

Power semiconductor module having a half-bridge configuration

A semiconductor device has first, second, and third connecting leads (), whose respective base points () have centroids (). The connecting leads are arranged wherein an angle (&#x3b1;) between a first line drawn between the centroids () of the base points () of first lead () and third lead () and a second line drawn between the centroids () of the base points () of second lead () and third lead () is 20&#xb0; maximum. In addition, a semiconductor module may incorporate two or more semiconductor devices which are connected electrically in parallel.

Growing community of inventors

Warstein, Germany

Oliver Schilling