Cypress Semiconductor Corporation

On Semiconductor Trading, Ltd.

Oliver Pohland

Vladimir Korobov

Jeong Soo Byun

Helmut Puchner

Igor Polishchuk

Yanzhong Xu

Kaichiu Wong

Yangzhong Xu

Jeong-Yeop Nahm

A method and apparatus for a reverse metal-insulator-metal (MIM) capacitor. The apparatus includes a lower metal layer, a bottom electrode, and an upper metal layer. The lower metal layer is disposed above a substrate layer. The bottom electrode is disposed above the lower metal layer and coupled to the lower metal layer. The upper metal layer is disposed above the bottom electrode. The upper metal layer comprises a top electrode of a metal-insulator-metal (MIM) capacitor.

Reverse MIM capacitor

An image sensor having shield structures and methods of forming the same are provided. Generally, the image sensor includes: (i) substrate having at least one photosensitive element formed therein; (ii) a dielectric layer overlying the substrate and the photosensitive element; and (iii) an annular reflective waveguide disposed in the dielectric layer above the photosensitive element to reduce cross-talk between adjacent elements of the sensor while increasing sensitivity of the sensor. In certain embodiments, the sensor further includes a photoshield disposed in the dielectric above the photosensitive element and about the waveguide to further reduce the possibility of cross-talk. Other embodiments are also disclosed.

Method for forming image sensor with shield structures

Image sensor with a reflective waveguide

A regulated circuit having a number of metal-oxide-semiconductor field effect transistors (MOS FETs) and a method for using the same are provided to reduce Negative Bias Temperature Instability degradation of the MOS FETs on the circuit. In one embodiment, the method involves steps of: (i) detecting degradation in performance of at least one of the MOS FETs causing a shift in threshold voltage (V) of the MOS FET; and (ii) if the shift in Vexceeds a predetermined value, forward biasing the MOS FETs, thereby reducing or reversing the shift in V. Optionally, the method includes an initial step of determining if the circuit is in a non-dynamic operating mode before forward biasing the MOS FETs. Other embodiments are also disclosed.

Method and circuit for reducing degradation in a regulated circuit

Methods are provided for manufacturing a semiconductor circuit on a substrate of a first conductivity type to control threshold voltages of devices in the circuit. One method involves: (i) forming a photoresist mask on a surface of the substrate defining a well boundary around an area in which a well is to be formed; (ii) implanting ions into the substrate to form a well of a second conductivity type, wherein a region proximal to the well boundary is effected by lateral scattering of the ions by the mask; and (iii) forming a channel of a device, at least a portion of the channel formed in the region proximal to the well boundary, wherein the ions are implanted at an acute angle to the surface substrate to shadow the portion of the channel from at least some of the ions implanted to form the channel. Other embodiments are also provided.

Method of threshold voltage control in metal-oxide-semiconductor devices

In one embodiment, a method of fabricating a transistor for a memory cell includes the steps of performing a counter doping implant before or after a source/drain implant. The counter doping implant may comprise one or more implant steps that move a metallurgical junction formed by a well and a highly doped region closer to a surface of the substrate. The counter doping implant may also increase the concentration of the dopant of the well. The counter doping implant and the source/drain implant may be performed using the same mask. Transistors fabricated using embodiments of the present invention may be employed in memory cells to reduce soft error rates.

Method for reducing soft error rates of memory cells

Methods for fabricating diffusion regions having steep concentration profiles within MOS devices while minimizing junction capacitance degradation are provided. In particular, methods are provided which include patterning a gate structure upon a semiconductor substrate and subsequently etching a recess in exposed portions of the substrate. In some cases, the method includes forming a first dopant region within the exposed portions prior to etching the recess. The method may additionally or alternatively include implanting a second set of dopants into portions of the semiconductor substrate bordering the recess. In either case, the method includes growing an epitaxial layer within the recess and implanting a third set of dopants into the semiconductor topography to form a second dopant region extending to a depth at least within the epitaxial layer. A resulting semiconductor topography includes a source/drain region comprising an upper portion consisting essentially of first dopants of a first conductivity type.

Methods for forming super-steep diffusion region profiles in MOS devices and resulting semiconductor topographies

Contact structures, methods for forming contact structures, and masks for forming contact structures are disclosed. According to one embodiment a contact hole ( ) may be formed with a contact hole mask ( ) that may have a generally rectangular shape and include corner extensions ( - to - ) and side indents ( - to - ). A long side of a contact hole ( ) may be aligned in the same direction as an active area ( ). A contact hole ( ) may be situated between a first portion ( - ) and a second portion ( - ) of an intermediate structure ( ). Alternate embodiments can include a &ldquo;cactus&rdquo; shaped intermediate structure ( ) that may be formed with an intermediate structure mask having corner indents ( ).

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San Jose, CA, United States of America

Oliver Pohland