Texas Instruments Incorporated Deutschland, Gmbh

Texas Instruments Corporation

Oliver Piepenstock

Ulrich Schacht

Frank Gelhausen

Andreas Bock

Gerd Schuppener

Mustafa Ulvi Erdogan

Bhavesh G Bhakta

Dirk Muentefering

The present disclosure relates to an apparatus comprising at least two operational amplifiers, a first and a second current input, at least one voltage output, and at least two resistors, wherein a first current source is connectable to the first current input, and a test current source is connectable to the second current input, and wherein the first current input is connected to an inverting input of the first operational amplifier and the second current input is connected to an inverting input of the second operational amplifier, and a first feedback resistor is connected between the output and the inverting input of the first operational amplifier and a second feedback resistor is connected between the output and the inverting input of the second operational amplifier, and wherein the voltage output is connected to the outputs of the first and the second operational amplifier.

Apparatus and method for testing of successful operation of transimpedance amplifiers

Improved preamplifier circuits for converting single-ended input current signals to differential output voltage signals, including first and second transimpedance amplifiers with input transistors operating according to bias currents from a biasing circuit, output transistors and adjustable feedback impedances modified using an automatic gain control circuit, as well as a reference circuit controlling the bias currents according to an on-board reference current and the single-ended input or the differential output voltage signals from the transimpedance amplifiers.

Apparatus and method for transimpedance amplifiers with wide input current ranges

The present disclosure relates to an Apparatus comprising at least one resistive voltage divider and at least two inverters, wherein the resistive voltage divider is coupled between a first supply potential terminal (VDD) and a second supply potential terminal (VSS), wherein the voltage divider comprises a first resistor, a second resistor, a third resistor and a fourth resistor being serially connected, and wherein a first connection point of the second resistor and the third resistor is connected to an voltage input, and a second connection point of the first resistor and the second resistor is connected to the input side of a first inverter, and a third connection point of the third resistor and the fourth resistor is connected to the input side of a second inverter, wherein the first inverter and the second inverter are configured to provide a first output voltage if a first voltage is applied to the voltage input, and the first inverter and the second inverter are configured to provide a second output voltage if a second voltage is applied to the voltage input, and the first inverter is configured to provide the second output voltage and the second inverter is configured to provide the first output voltage if an open input is applied to the voltage input as well as a method.

Apparatus and method for three-level input detection

A buffer is provided. The buffer includes a first switch and a second switch coupled in series at a first output node, a third switch and a fourth switch coupled in series at a second output node, a first current source and a second current source. The first current source is coupled with one side to the first switch and the third switch and with another side to a first supply voltage, the second current source is coupled with one side to the second switch and the fourth switch and with a second side to a second supply voltage. The first current source is configured to adjust an output swing in a first operation mode and in a second operation. The second current source is configured to adjust a common mode voltage level of the output signal in the first operation mode and to provide maximum series resistance in the second operation mode.

Electronic device and method for buffering

The invention relates to an electronic device that includes a plurality of buffers and a phase locked loop. For each buffer a fractional divider is provided which is coupled to receive the output from the phase locked loop and configured to feed a divided output signal to a respective buffer. A spread spectrum clock control logic stage in the spread spectrum clock (SSC) is provided which is configured to individually adjust a value of the division of each fractional divider in order to individually and independently modulate the output signal of each fractional divider according to a spread spectrum modulation scheme.

Electronic device and method for spread spectrum clock (SSC) modulation

Here, a driver for an light emitting diode (LED) is provided. Within this driver, several differential pairs of bipolar transistors are employed in an input stage and output stage along with a control loop. Collectively, these components operate together to drive the LED with a low headroom voltage while still achieving high driver performance in terms of edge speed and jitter.

Growing community of inventors

Lower Saxony, Germany

Oliver Piepenstock