Siemens Aktiengesellschaft

Oliver Kiehl

Dominique Savignac

Rudolf Koch

Michael A Killian

Diether Sommer

Klaus J Lau

Jens Sauerbrey

Fergal Bonner

A semiconductor memory device is disclosed which includes an input terminal for receiving, and an output terminal for producing a data word, each having a predetermined number of bits. An internal memory array stores a plurality of error correcting encoded codewords each encoding more than one data word. An error correcting encoder is coupled between the input terminal and the memory array for generating an error correcting encoded codeword, encoding the received data word, and storing the codeword in the internal memory array. An error correcting decoder is coupled between the internal memory array and the output terminal to retrieve an error correction encoded codeword from the internal memory array, correct any detected errors, and produce one of the more than one data words encoded in the retrieved codeword at the output terminal.

Flexible ECC/parity bit architecture

A fully differential resistor-string digital-to-analog converter wherein a resistor network having half the number of resistors of an otherwise standard digital-to-analog convertor of this type is enabled with the assistance of a first decoder, a second decoder and a subtraction unit thus reducing the required chip area and the overall switching time.

Fully differential digital-to-analog converter with a low number of

A redundant circuit configuration for an integrated semiconductor memory has normal and redundant memory cells, in which addresses of arbitrary groups of memory cells of the memory are formed from a first partial address and a second partial address. M fixedly programmable address circuits, where M.gtoreq.1, are each assigned to one of the first partial addresses. Each fixedly programmable address circuit in an activated state has the second partial address of a group of normal memory cells to be replaced and has a first output at which an activation signal is applied in the activated state of the address circuit if the first partial address applied to the circuit configuration matches the first partial address assigned to the address circuit. One address comparator is common to all of the address circuits and has a first output. The comparator compares the second partial address stored in memory in one of the address circuits with the applied second partial address, at the applied activation signal of the one address circuit. The comparator supplies an enable signal at the first output of the address comparator if the two partial addresses match. Redundance decoders are triggered by the enable signal.

Redundant circuit configuration for an integrated semiconductor memory

A current mirror includes first through eighteenth transistors. The load paths of the first and second transistors are in series for carrying an input current to a first supply potential. The control terminals of the first through eighth transistors receive the input current. The load paths of the fourth, third, ninth and tenth transistors are in series between the first and a second supply potential. The third and ninth transistors form a tap being connected to the control terminals of the ninth, tenth, eleventh, twelfth and thirteenth transistors. The load paths of the fifth, sixth, eleventh and fourteenth transistors are in series between the first and second supply potentials. The sixth and eleventh transistors form a tap being connected to the control terminals of the fourteenth through sixteenth transistors. The load paths of the seventeenth, seventh, twelfth and fifteenth transistors are in series between the first and second supply potentials. The seventh and twelfth transistors form a tap being connected to the control terminals of the seventeenth and eighteenth transistors. The load paths of the eighteenth and eighth transistors are in series for tapping a first output current proportional to the input current from the first supply potential. The load paths of the sixteenth and thirteenth transistors are in series for tapping a second output current equal to the first from the second supply potential. The ninth through sixteenth transistors are of one, and the seventeenth, eighteenth and first through eighth transistors being of the other, conduction type.

Current mirror

A current mirror includes first and second transistors each having a control terminal and a load path with two terminals. The control terminals of the first and second transistors and one of the terminals of the load path of the first transistor receive a first input current. Third, fourth and fifth transistors each have a control terminal and a load path with two terminals. The control terminals of the third, fourth and fifth transistors and one of the terminals of the load path of the third transistor receive a second input current of equal magnitude to the first input current. One of the terminals of the load path of the fifth transistor supplies an output current proportional to the two input currents. The other of the terminals of the load paths of the third and fifth transistors are each connected to one terminal of the load path of a respective one of the fourth and second transistors. The other of the terminals of the load paths of the first, second and fourth transistors are connected to a common reference point.

A circuit configuration for adjusting the quadrature-axis current component of a push-pull output stage has two transistors of opposed conduction type and is triggered by an input signal. A variable being proportional to the quadrature-axis current component of the push-pull output stage is derived from a comparison circuit. A final control element adjusts the quadrature-axis current components of the push-pull output stage and of the comparison circuit for matching the variable to a reference variable.

Circuit configuration for adjusting the quadrature-axis current

A decoded source sense amplifier in which the column select signal is shaped so that it turns on bit select transistors at a predetermined time after the source electrodes of the sense amplifier are connected to ground, so as to give the sense amplifier time to latch before it is coupled to external bit lines.

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Munich, Germany

Oliver Kiehl