Infineon Technologies Austria Ag

Infineon Technologies Ag

Oliver Häberlen

Gerhard Prechtl

Clemens Ostermaier

Gilberto Curatola

Walter Rieger

Ralf Otremba

Klaus Schiess

Manfred Kotek

Gianmauro Pozzovivo

Martin Pölzl

Horst Schäfer

Franz Hirler

Roland Rupp

Oliver Blank

Albert Birner

Guenther Ruhl

Wolfgang Lehnert

Helmut Brech

Dirk Ahlers

Rudolf Berger

Adrian Finney

Eric G Persson

Gerhard Nöbauer

Marius Aurel Bodea

Reenu Garg

Guanmauro Pozzovivo

Joachim Schönle

An electronic circuit and a method are disclosed. The electronic circuit includes: a first transistor device having a load path between a first load path node and a second load path node; and a clamping circuit connected to the load path of the first transistor device. The clamping circuit includes: a second transistor device having a load path connected in parallel with the load path of the first transistor device, and a control node; and a drive circuit configured to drive the second transistor device. The drive circuit includes a clamping element and a resistor connected in series between the first and second load path nodes of the first transistor device. The drive circuit is configured to drive the second transistor device dependent on a voltage across the resistor. The first transistor device and the clamping circuit are integrated in a same semiconductor die.

Electronic circuit with a transistor device and a clamp circuit and method

In an embodiment, a semiconductor device is provided that includes a lateral transistor device having a source, a drain and a gate, and a monolithically integrated capacitor coupled between the gate and the drain.

Semiconductor device having a lateral transistor device and an inverter that includes the semiconductor device

A high-electron-mobility semiconductor device includes: a buffer region having first, second and third cross-sections forming a stepped lateral profile, the first cross-section being thicker than the third cross-section and comprising a first buried field plate disposed therein, the second cross-section interposed between the first and third cross-sections and forming oblique angles with the first and third cross-sections; and a barrier region of substantially uniform thickness extending along the stepped lateral profile of the buffer region, the barrier region being separated from the first buried field plate by a portion of the buffer region. The buffer region is formed by a first semiconductor material and the barrier region is formed by a second semiconductor material. The first and second semiconductor materials have different band-gaps such that an electrically conductive channel including a two-dimensional charge carrier gas arises at an interface between the buffer and barrier regions due to piezoelectric effects.

High-electron-mobility transistor having a buried field plate

A semiconductor device includes a group III-semiconductor-nitride-based channel layer, a group III-semiconductor-nitride-based barrier layer formed on the channel layer, a two-dimensional electron gas channel formed in the channel layer, a first current electrode and a second current electrode formed on the barrier layer and laterally spaced from each other, and a gate structure formed on the barrier layer between the first and second current electrodes. The barrier layer has a symmetrically shaped recess between the first and second current electrodes, the symmetrically shaped recess including a first recess portion formed in a part of an upper surface of the barrier layer and a second recess portion formed within the first recess portion. The gate structure includes a group III-semiconductor-nitride-based doped layer that fills the symmetrically shaped recess and an electrically conductive gate electrode formed on an upper side of the doped layer that is opposite from the barrier layer.

Semiconductor device

A semiconductor disk of a first crystalline material, which has a first lattice system, is bonded on a process surface of a base substrate, wherein a bonding layer is formed between the semiconductor disk and the base substrate. A second semiconductor layer of a second crystalline material with a second, different lattice system is formed by epitaxy on a first semiconductor layer formed from the semiconductor disk.

Method of manufacturing semiconductor devices by bonding a semiconductor disk on a base substrate, composite wafer and semiconductor device

In an embodiment, a method includes forming an intentionally doped superlattice laminate on a support substrate, forming a Group III nitride-based device having a heterojunction on the superlattice laminate layer, and forming a charge blocking layer between the heterojunction and the superlattice laminate.

Methods of forming substrate structures and semiconductor components

A method of manufacturing a semiconductor die includes forming a semiconductor body on a substrate. The semiconductor body has a periphery which is devoid of active devices and terminates at an edge face of the semiconductor die. The semiconductor body includes a first III-nitride semiconductor layer and a plurality of second III-nitride semiconductor layers below the first III-nitride semiconductor layer. The method further includes forming an uninsulated connection structure which extends vertically in the periphery of the semiconductor body and provides a vertical leakage path for at least some of the second III-nitride semiconductor layers either to the substrate or to a metallization layer disposed above the semiconductor body, but not to both. Additional semiconductor die manufacturing methods are provided.

Method of forming a vertical potential short in a periphery region of a III-nitride stack for preventing lateral leakage

A semiconductor die includes a substrate and a semiconductor body supported by the substrate and having a periphery which is devoid of active devices and terminates at an edge face of the semiconductor die. The semiconductor body includes a first III-nitride semiconductor layer and a plurality of second III-nitride semiconductor layers below the first III-nitride semiconductor layer. An uninsulated connection structure extends vertically in the periphery of the semiconductor body and provides a vertical leakage path for at least some of the second III-nitride semiconductor layers to the substrate, to a metallization layer disposed above the substrate, or to both. A corresponding method of manufacturing the semiconductor die is also described.

Vertical potential short in the periphery region of a III-nitride stack for preventing lateral leakage

A Group III-nitride-based enhancement mode transistor includes a multi-heterojunction fin structure. A first side face of the multi-heterojunction fin structure is covered by a first p-type Group III-nitride layer, and a second side face of the multi-heterojunction fin structure is covered by a second p-type Group III-nitride layer.

Group III-nitride-based enhancement mode transistor having a multi-heterojunction fin structure

In an embodiment, a substrate structure includes a support substrate, a buffer structure arranged on the support substrate, the buffer structure including an intentionally doped superlattice laminate, an unintentionally doped first Group III nitride layer arranged on the buffer structure, a second Group III nitride layer arranged on the first Group III nitride layer forming a heterojunction therebetween, and a blocking layer arranged between the heterojunction and the buffer structure. The blocking layer is configured to block charges from entering the buffer structure.

Substrate structure, semiconductor component and method

A semiconductor device includes a semiconductor body including a plurality of compound semiconductor layers and a two-dimensional charge carrier gas channel region formed in one of the compound semiconductor layers. The semiconductor device further includes a contact structure disposed in the semiconductor body. The contact structure includes a metal region and a doped region. The metal region extends into the semiconductor body from a first side of the semiconductor body to at least the compound semiconductor layer which includes the channel region. The doped region is formed in the semiconductor body between the metal region and the channel region so that the channel region is electrically connected to the metal region through the doped region.

Contact structures for compound semiconductor devices

A method of manufacturing an electronic component includes applying solder paste to at least one electrically conductive portion of a package, applying a high-voltage depletion-mode transistor onto the solder paste, applying a low-voltage enhancement-mode transistor onto the solder paste, applying solder paste onto the high-voltage depletion-mode transistor, applying solder paste onto the low-voltage enhancement-mode transistor, applying an electrically conductive member onto the solder paste on the high-voltage depletion-mode transistor and onto the solder paste on the low-voltage enhancement-mode transistor to form an assembly, and heat treating the assembly to produce an electrical connection between the high-voltage depletion-mode transistor and the low-voltage enhancement-mode transistor via the electrically conductive member.

Method of manufacturing an electronic component

In an embodiment, an electronic device includes a semiconductor layer having a surface, a gate and a first current electrode on the surface and a dielectric layer extending between the gate and the first current electrode and including charged ions having a predetermined charge profile.

Electronic device

A transistor device includes a compound semiconductor body having a first surface and a two-dimensional charge carrier gas disposed below the first surface in the compound semiconductor body. The transistor device further includes a source in contact with the two-dimensional charge carrier gas and a drain spaced apart from the source and in contact with the two-dimensional charge carrier gas. A first passivation layer is in contact with the first surface of the compound semiconductor body, and a second passivation layer is disposed on the first passivation layer. The second passivation layer has a different etch rate selectivity than the first passivation layer. A gate extends through the second passivation layer into the first passivation layer.

Compound semiconductor transistor with self aligned gate

An electronic component includes a high-voltage depletion-mode transistor, a low-voltage enhancement-mode transistor arranged adjacent and spaced apart from the high-voltage depletion-mode transistor, and an electrically conductive member electrically coupling a first current electrode of the high-voltage depletion-mode transistor to a first current electrode of the low-voltage enhancement-mode transistor. The electrically conductive member has a sheet-like form.

Growing community of inventors

Villach, Austria

Oliver Häberlen