Forschungsverbund Berlin E.v.

Oliver Hilt

Hans-Joachim Würfl

Hans-Joachim Wuerfl

Rimma Zhytnytska

The invention relates to semiconductor components, in particular to a scalable construction for lateral semiconductor components having high current-carrying capacity. A transistor cell according to the invention comprises a control electrode (), a plurality of source fields () and a plurality of drain fields (). The control electrode completely encloses at least one of the source fields or drain fields. A transistor according to the invention comprises a plurality of transistor cells on a substrate, each of which comprises a source contact field () and/or a drain contact field (). The source contact fields are conductively connected to each other on the other side of the substrate and the drain contact fields are likewise conductively connected to each other on the other side of the substrate. The method according to the invention for producing a transistor comprises the following steps: providing a substrate; forming a plurality of transistor cells on the substrate, each of which comprises a control electrode, a plurality of source fields and a plurality of drain fields; conductively connecting the control electrodes to each other; forming a source contact field and/or a drain contact field in each transistor cell; conductively connecting the source contact fields of each transistor cell to a source contact field; conductively connecting the drain fields of each transistor cell to a drain contact field; forming at least one bump () on each of the source contact fields and on each of the drain contact fields; providing a circuit board; conductively connecting the bumps of the source contact fields to each other by means of conductive tracks on the circuit board; and conductively connecting the bumps of the drain contact fields to each other by means of conductive tracks on the circuit board. The arrangement of the bumps and the conductive tracks on the circuit board makes a low semiconductor surface assignment by wiring possible. The arrangement according to the invention of the source fields, drain fields and control electrodes relative to the bumps makes a low heat resistance possible between the active transistor regions and the bumps.

Scalable construction for lateral semiconductor components having high current-carrying capacity

This invention relates to a semiconductor layer structure. The semiconductor layer structure described includes a substrate and a buffer layer deposited onto the substrate. The semiconductor layer structure is characterized in that a drain voltage threshold lower than the breakdown voltage threshold is determined by isolating ions that are selectively implanted in just one region of the substrate into the substrate, wherein charge can dissipate from the one contact through the buffer layer towards a substrate region without isolating ions, if the one potential deviates from the other at least by the drain voltage threshold, and wherein the substrate region without isolating ions is located underneath the one contact. The semiconductor layer structure described allows dissipation of currents induced by induction in blocking active structures without damaging the active structures.

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Schöneiche, Germany

Oliver Hilt