Infineon Technologies Austria Ag

Infineon Technologies Ag

Oliver Haeberlen

Gerhard Prechtl

Walter Rieger

Clemens Ostermaier

Gilberto Curatola

Franz Hirler

Klaus Schiess

Joachim Krumrey

Ralf Otremba

Martin Poelzl

Anton Mauder

Andreas Peter Meiser

Maximilian Roesch

Matteo-Alessandro Kutschak

Thomas Detzel

Lutz Goergens

Johannes Schoiswohl

Markus Zundel

Hans Weber

Martin Henning Vielemeyer

Rudolf Zelsacher

Stefan Sedlmaier

Manfred Kotek

Stefan Kramp

Hans Peter Felsl

Simone Lavanga

Gianmauro Pozzovivo

Josef Maerz

Milko Paolucci

Joost Larik

Fabian Reiher

Manuel Stabentheiner

Ralf Erichsen

Nikolaus Bott

Hans-Joachim Schulze

Ralf Siemieniec

Gerald Deboy

Eung San Cho

Oliver Blank

Christoph Kadow

Michael Treu

Alexander Breymesser

Stephan Voss

Anthony Sanders

Erich Griebl

Paul Ganitzer

Uli Hiller

Gerald Lackner

Michael Stadtmueller

Eric G Persson

Guenter Denifl

Andrew Wood

Andreas Moser

Jan Ropohl

Erwin Bacher

Franz Auerbach

Mathias Born

Reenu Garg

Balamurugan Karunamurthy

Maria Reiner

Peter Lagger

Josef Schellander

Sonja Krumrey, Legal Representative

Kathrin Rueschenschmidt

A semiconductor device includes: a device formed in a III-V semiconductor body; metal layer(s) above the III-V semiconductor body; an interlayer dielectric adjacent each metal layer; vias electrically connecting each metal layer to the device formed in the III-V semiconductor body; a passivation layer touching and being supported by a top surface of the III-V semiconductor body, the lowermost interlayer dielectric touching and being supported by a top surface of the passivation layer, the passivation layer being an ineffective barrier against diffusion of water, water ions, sodium ions and potassium ions into the III-V semiconductor body; and a barrier interposed between a first oxide layer and a second oxide layer of the lowermost interlayer dielectric. The barrier is configured to prevent water, water ions, sodium ions and potassium ions from diffusing into the first oxide layer of the lowermost interlayer dielectric and which is immediately below the barrier.

Water and ion barrier for III-V semiconductor devices

A method includes providing a semiconductor body including a plurality of two-dimensional charge carrier gas channels, forming a gate fin by forming a pair of gate trenches in an upper surface of the semiconductor body, the pair of gate trenches exposing each one of two-dimensional charge carrier gas channels, providing source and drain contacts that are electrically connected to each one of the plurality of two-dimensional charge carrier gas channels, providing a gate structure that is configured to control a conductive connection between the source and drain contacts, wherein providing the gate structure includes forming a layer of doped type III-nitride semiconductor material that covers the gate fin and extends into the gate trenches, and forming a conductive gate electrode on top of the layer of doped type III-nitride semiconductor material.

High electron mobility transistor with doped semiconductor region in gate structure

In an embodiment, a Group III nitride-based transistor device, includes a first Group III nitride barrier layer arranged on a Group III nitride channel layer, the first Group III nitride barrier layer and the Group III nitride channel layer having differing bandgaps and forming a heterojunction capable of supporting a two-dimensional charge gas. A source, a gate and a drain are on an upper surface of the first Group III nitride barrier layer. A gate recess extends from the upper surface of the first Group III nitride barrier layer into the first Group III nitride barrier layer. A p-doped Group III nitride material arranged in the gate recess has a first extension extending on the upper surface of the first Group III nitride barrier layer towards the drain. The first extension has a length l, and 0 nm≤l≤200 nm.

Group III nitride-based transistor device

A semiconductor device is described. In one embodiment, the device includes a Group-III nitride channel layer and a Group-III nitride barrier layer on the Group-III nitride channel layer, wherein the Group-III nitride barrier layer includes a first portion and a second portion, the first portion having a thickness less than the second portion. A p-doped Group-III nitride gate layer section is arranged at least on the first portion of the Group-III nitride barrier layer and a gate contact formed on the p-doped Group-III nitride gate layer.

Nitride semiconductor device

An enhancement mode Group III nitride-based transistor device includes a body having a first surface and a Group III nitride barrier layer arranged on a Group III nitride channel layer and forming a heterojunction therebetween. A first cell field includes transistor cells and an edge region. Each transistor cell includes source, gate and drain fingers extending substantially parallel to one another on the first surface in a longitudinal direction. The gate finger, arranged laterally between the source and drain fingers, includes a p-doped Group III nitride finger arranged between a metallic gate finger and the first surface. The edge region surrounds the transistor cells and includes an edge termination structure having an isolation ring and a p-doped Group III nitride runner. The isolation ring locally interrupts the heterojunction. The runner, extending transversely to the longitudinal direction, is located laterally between the isolation ring and an end of the drain finger.

Enhancement mode transistor device

In an embodiment, a semiconductor device is provided that includes a lateral transistor device having a source, a drain and a gate, and a monolithically integrated capacitor coupled between the gate and the drain.

Semiconductor device and inverter

Enhancement mode Group III nitride-based transistor device

In an embodiment, a Group III nitride-based transistor device, includes a first. Group III nitride barrier layer arranged on a Group III nitride channel layer, the first Group III nitride barrier layer and the Group III nitride channel layer having differing bandgaps and forming a heterojunction capable of supporting a two-dimensional charge gas. A source, a gate and a drain are on an upper surface of the first Group III nitride barrier layer. A gate recess extends from the upper surface of the first. Group III nitride barrier layer into the first Group III nitride barrier layer. A p-doped Group III nitride material arranged in the gate recess has a first extension extending on the upper surface of the first Group III nitride barrier layer towards the drain. The first extension has a length l, and 0 nm&#x2264;l&#x2264;200 nm.

Group III nitride-based transistor device and method of fabricating a gate structure for a group III nitride-based transistor device

A transistor device includes a gate fin that is a segment of a semiconductor body disposed between a pair of gate trenches formed in an upper surface of the semiconductor body, a plurality of two-dimensional charge carrier gas channels disposed at different vertical depths within the gate fin, source and drain contacts arranged on either side of the gate fin in a current flow direction of the gate fin, the source and drain contacts each being electrically connected to each one of the two-dimensional charge carrier gas channels, and a gate structure that is configured to control a conductive connection between the source and drain contacts. The gate structure includes a region of doped type III-nitride semiconductor material that covers the gate fin and extends into the gate trenches, and a conductive gate electrode formed over the region of doped type III-nitride semiconductor material.

A semiconductor device includes a transistor in a semiconductor body having a main surface. The transistor includes a source region; a drain region; a body region; a drift zone; a gate electrode at the body region, the body region and the drift zone being disposed along a first direction between the source region and the drain region, and the first direction being parallel to the main surface; a field plate disposed in each of a plurality of field plate trenches, each of the field plate trenches having a longitudinal axis extending along the first direction; and a field dielectric layer between the field plate and the drift zone, a thickness of the field dielectric layer at a bottom of each of the field plate trenches gradually increases along the first direction, the thickness being measured along a depth direction of the plurality of field plate trenches.

Semiconductor device comprising a gradually increasing field dielectric layer and method of manufacturing a semiconductor device

A semiconductor device includes a heterojunction semiconductor body including a first and second type III-V semiconductor layers with different bandgaps such that a first two-dimensional charge carrier gas forms at an interface between the two layers. The second type III-V semiconductor layer includes a thicker section and a thinner section. A first input-output electrode is on the thicker section and is in ohmic contact with the first two-dimensional charge carrier gas. A second input-output electrode is formed on the thinner section and is in ohmic contact with the first two-dimensional charge carrier gas. A gate structure is formed on the thinner section and is configured to control a conductive connection between the first and second input-output electrodes. The gate structure is laterally spaced apart from a transition between the thicker and thinner sections of the second type III-V semiconductor layer.

High electron mobility transistor with dual thickness barrier layer

A device includes a driver circuit, a first semiconductor chip monolithically integrated with the driver circuit in a first semiconductor material, and a second semiconductor chip integrated in a second semiconductor material. The second semiconductor material is a compound semiconductor.

Device including a semiconductor chip monolithically integrated with a driver circuit in a semiconductor material

In accordance with an embodiment, a circuit includes a first gallium nitride (GaN) transistor comprising a drain coupled to a drain node, a source coupled to a source node, and a gate coupled to a gate node; and a second GaN transistor comprising a drain coupled to the drain node, a source coupled to a first power source node configured to be coupled to a first capacitor.

System and method for a GaN-based start-up circuit

Growing community of inventors

Villach, Austria

Oliver Haeberlen