Nvidia Corporation

Oliver Giroux

Jack H Choquette

Shirish C Gadre

Alexander Lev Minkin

Ronny Krashinsky

Manan Patel

Mark William Stephenson

John Tran

Daniel Robert Johnson

Alan Kaatz

Jeff Schottmiller

Sana Damani

Michael Patrick McKeown

A parallel processing unit comprises a plurality of processors each being coupled to a memory access hardware circuitry. Each memory access hardware circuitry is configured to receive, from the coupled processor, a memory access request specifying a coordinate of a multidimensional data structure, wherein the memory access hardware circuit is one of a plurality of memory access circuitry each coupled to a respective one of the processors; and, in response to the memory access request, translate the coordinate of the multidimensional data structure into plural memory addresses for the multidimensional data structure and using the plural memory addresses, asynchronously transfer at least a portion of the multidimensional data structure for processing by at least the coupled processor. The memory locations may be in the shared memory of the coupled processor and/or an external memory.

Method and apparatus for efficient access to multidimensional data structures and/or other large data blocks

Convergence of threads executing common code sections is facilitated using instructions inserted at strategic locations in computer code sections. The inserted instructions enable the threads in a warp or other group to cooperate with a thread scheduler to promote thread convergence.

Convergence among concurrently executing threads

Growing community of inventors

Santa Clara, CA, United States of America

Oliver Giroux