Infineon Technologies Ag

Oliver Frank

Jochen Oliver Schrattenecker

Florian Starzer

Rainer Stuhlberger

Guenter Haider

Thomas Sailer

Michael Kropfitsch

Karl Dominizi

Peter Bogner

Herbert Knapp

Hao Li

Herbert Jaeger

Helmut Kollmann

Georg Krebelder

Christoph Wagner

Vincenzo Fiore

Jonas Wursthorn

Jonas Kammerer

Klaus Standner

Sebastian Pointner

Ralf Reiterer

Harald Kainmueller

Alexander Kaineder

Stefan Zielke

Christoph Hazott

Bruno Mariacher

Michael Platzer

Otto Pfabigan

A method is disclosed use with a circuit device that includes a circuit having a predetermined voltage-current characteristic and a detector configured to detect a voltage-current relation of the circuit. The method includes using the detector to detect the voltage-current relation of the circuit, and indicating if the detected voltage-current relation differs from the predetermined voltage-current characteristic. A circuit device includes a circuit having a predetermined voltage-current characteristic, and a detector configured to detect a voltage-current relation of the circuit. The circuit device is configured to indicate if the detected voltage-current relation differs from the predetermined voltage-current characteristic.

Health monitoring of a circuit

A method for producing a semiconductor device is described. In accordance with one example embodiment, the method comprises providing a virtual DUT in the form of a behavior model of the semiconductor device and developing at least one test in a test development environment for an automatic test equipment (ATE). In this case, commands are generated by means of the test development environment, which commands are converted into test signals by means of a software interface, which test signals are fed to the virtual DUT and are processable by the latter. The software interface processes response signals of the virtual DUT and reports information dependent on the response signals back to the test development environment.

Method for producing a semiconductor device by means of computer-aided development of test scenarios

A radar device comprises a test signal generator including a digital harmonic oscillator that generates a digital oscillator signal with a first spectral component; a first digital-to-analog-converter that generates an analog oscillator signal based on the digital oscillator signal. Furthermore, the radar device comprises at least one radar channel receiving the analog oscillator signal during one or more self-tests.

RF receiver with built-in test capabilities

A compound may include a set of integrated circuits. An integrated circuit, of the set of integrated circuits, may include calibration standards integrated at a silicon layer of the integrated circuit. The integrated circuit may be included in a package, and a calibration standard, of the calibration standards, may be available to at least one port of a set of ports of the integrated circuit.

Scattering parameter calibration to a semiconductor layer

One exemplary embodiment of the present invention relates to a circuit that includes at least one RF signal path for an RF signal and at least one power sensor, which is coupled to the RF signal path and configured to generate a sensor signal representing the power of the RF signal during normal operation of the circuit. The circuit further includes a circuit node for receiving an RF test signal during calibration operation of the circuit. The circuit node is coupled to the at least one power sensor, so that the at least one power sensor receives the RF test signal additionally or alternatively to the RF signal and generates the sensor signal as representing the power of the RF test signal.

RF front-end with power sensor calibration

A test set-up for testing a system-in package with an integrated antenna is described herein. According to one exemplary embodiment, the test set-up includes a carrier with an RF probe arranged thereon and a test socket with resilient electric contacts. The test socket is mounted on the carrier and provides an electric contact to interconnects of the package when it is placed on the test socket. The test socket has an opening which is arranged superjacent to the RF probe.

Device, system and method for automatic test of integrated antennas

A radar sensor includes a mixer configured to receive an radio frequency (RF) input signal to down-convert the RF input signal into a base-band or intermediate frequency (IF) band, an analog-to-digital converter (ADC), and a signal processing chain coupled between the mixer and the ADC. The radar sensor further includes an oscillator circuit that is configured to generate a test signal. The ADC is coupled to an output of the signal processing chain, and is configured to generate a digital signal by digitizing an output signal of the signal processing chain, the output signal being derived from the test signal. The radar sensor further includes a digital signal processing circuit coupled to the ADC downstream thereof, the digital signal processing circuit being configured to perform a spectral analysis on frequency values of the digital signal.

RF receiver with built-in self-test function

An integrated circuit is described herein. According to one or more embodiments, the integrated circuit includes a local oscillator with a voltage-controlled oscillator (VCO) that generates a local oscillator signal. Further, the integrated circuit includes a frequency divider coupled to the VCO downstream thereof. The frequency divider provides a frequency-divided local oscillator signal by reducing the frequency of the local oscillator signal by a constant factor. A first test pad of the integrated circuit is configured to receive a reference oscillator signal. Further, the integrated circuit includes a first mixer that receives the reference oscillator signal and the frequency-divided local oscillator signal to down-convert the frequency-divided local oscillator signal.

Integrated RF circuit with phase-noise test capability

A probe card for a wafer tester includes a mother card having a reinforcing element and at least one daughter card which is rigidly connected to the reinforcing element detachably. The mother card includes electrical contacts for producing an electrical connection with the wafer tester. The at least one daughter card includes electrical contact elements for making contact with an electrical circuit on a wafer. In addition, the mother card and the at least one daughter card are electrically detachably connected to one another via an electrical interface.

Probe card and method for producing a probe card

A radio frequency (RF) receive circuit is described herein. In accordance with one embodiment, the RF receive circuit includes a mixer configured to receive an RF input signal to down-convert the RF input signal into a base-band or intermediate frequency (IF) band, an analog-to-digital converter (ADC), and a signal processing chain coupled between the mixer and the ADC. The signal processing chain includes at least two circuit nodes. The RF receive circuit further includes an oscillator circuit that is configured to generate a test signal. The oscillator circuit is coupled to the signal processing chain and is configured to selectively feed the oscillator signal into one of the at least two circuit nodes.

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Linz, Austria

Oliver Frank