Infineon Technologies Austria Ag

Infineon Technologies Ag

Oliver Blank

Ralf Siemieniec

Franz Hirler

Li Juin Yip

Michael Hutzler

David Laforet

Martin Poelzl

Maximilian Roesch

Cedric Ouvrard

Uli Hiller

Martin Henning Vielemeyer

Minghao Jin

Johannes Baumgartl

Christof Altstaetter

Anton Mauder

Gerhard Noebauer

Rudolf Rothmaler

Markus Zundel

Walter Rieger

Stefan Sedlmaier

Heimo Hofer

Ingmar Neumann

Hans-Joachim Schulze

Andreas Peter Meiser

Christian Geissler

Bernhard Goller

Ravi Keshav Joshi

Robert Paul Haase

Rudolf Zelsacher

Thomas Feil

Joachim Krumrey

Sylvain Leomant

Adrian Finney

Andrew Christopher Graeme Wood

Michael Stadtmueller

Andrew Wood

Jan Ropohl

Harsh Naik

Adam Amali

Saurabh Roy

Alessandro Ferrara

Günter Denifl

Stefan Karner

Marcel Rene Mueller

Mathias Born

Andreas Kleinbichler

Germano Galasso

Oliver Haeberlen

Gerhard Prechtl

Werner Schustereder

Stefan Tegen

Giuseppe Bernacchia

Dirk Ahlers

Oliver Häberlen

Juergen Steinbrenner

Andreas Riegler

Oliver Hellmund

Wolfgang Jantscher

Stefan Kramp

Britta Wutte

Joerg Ortner

Daniel Maurer

Manfred Pippan

Cesar Augusto Braz

Elvir Kahrimanovic

Gerhard Nöbauer

Petra Fischer

Cédric Ouvrard

Marius Aurel Bodea

Riccardo Pittassi

Alexander Binter

Thomas Ralf Siemieniec

Timothy Henson

Waqas Mumtaz Syed

Kurt Pekoll

Laszlo Juhasz

Mario Kleindienst

Quaglino Roberto

Oliver Haeberlein

Nicole Schulze-Ollmert

Josef Liegl

Jürgen Bostjancic

Thomas Beyreder

Christof Altstätter

Lina Guo

Joachim Schönle

A semiconductor device is described. The semiconductor device includes: a semiconductor substrate; a trench formed in a first main surface of the semiconductor substrate; a field plate electrode in the trench and reaching a same level as the first main surface of the semiconductor substrate; an insulating material that separates the field plate electrode from the semiconductor substrate; and a material embedded in the field plate electrode. The field plate electrode is made of a different material than the material embedded in the field plate electrode. The trench adjoins a region of the semiconductor substrate through which current flows in a first direction during operation of the semiconductor device. Additional device embodiments and methods of producing the semiconductor device are also described.

Power semiconductor device having an electrode with an embedded material

An electronic circuit and a method are disclosed. The electronic circuit includes: a first transistor device having a load path between a first load path node and a second load path node; and a clamping circuit connected to the load path of the first transistor device. The clamping circuit includes: a second transistor device having a load path connected in parallel with the load path of the first transistor device, and a control node; and a drive circuit configured to drive the second transistor device. The drive circuit includes a clamping element and a resistor connected in series between the first and second load path nodes of the first transistor device. The drive circuit is configured to drive the second transistor device dependent on a voltage across the resistor. The first transistor device and the clamping circuit are integrated in a same semiconductor die.

Electronic circuit with a transistor device and a clamp circuit and method

The application relates to a semiconductor die including a device in an active area of the die. The device includes a field electrode region formed in a field electrode trench extending vertically into a semiconductor body. The field electrode region includes a first and a second field electrode stacked vertically above each other in the field electrode trench. An edge termination structure laterally between the active area and a lateral edge region of the die includes a first and a second shield electrode arranged laterally consecutive between the active area and the lateral edge region to stepwise decrease an electrical potential between the edge region and the active area.

Semiconductor die including an edge termination structure laterally between an active area and a lateral edge region of the die

A semiconductor device is described. The semiconductor device includes: a semiconductor substrate having an edge, an active area spaced inward from the edge, and an edge termination area laterally surrounding the active area; and a plurality of transistor cells formed in the active area, each transistor cell including a source region of a first conductivity type and a body region of a second conductivity type opposite the first conductivity type. The edge termination area includes a plurality of needle-shaped compensation trenches and is devoid of complete transistor cells. A body doping region of the second conductivity type and that includes the body regions of the transistor cells extends from the active area into the edge termination area. The body doping region in the edge termination area is physically and electrically isolated from the body doping region in the active area.

Edge termination structure for power transistor devices

The application relates to a semiconductor die having a semiconductor body including an active region, an insulation layer on the semiconductor body, and a sodium stopper formed in the insulation layer. The sodium stopper is arranged in an insulation layer groove which intersects the insulation layer vertically and extends around the active region. The sodium stopper is formed of a tungsten material that at least partly fills the insulation layer groove. Both the insulation layer groove and the tungsten material extend into the semiconductor body.

Semiconductor die having a sodium stopper in an insulation layer groove and method of manufacturing the same

The application relates to a semiconductor transistor device, having a source region, a body region including a channel region extending in a vertical direction, a drain region, a gate region arranged aside the channel region in a lateral direction, and a body contact region made of an electrically conductive material, wherein the body contact region forms a body contact area, the body contact region being in an electrical contact with the body region via the body contact area, and wherein the body contact area is tilted with respect to the vertical direction and the lateral direction.

Semiconductor transistor device having a titled body contact area and method of manufacturing the same

A semiconductor die is described. The semiconductor die includes a semiconductor body having an active region, a metallization formed on the semiconductor body, and a passivation formed on the metallization. The metallization includes at least one of a titanium layer, a titanium nitride layer, and a tungsten layer. The passivation includes a silicon oxide layer. Corresponding methods of manufacturing and using the semiconductor die are also described.

Semiconductor die and method of manufacturing the same

In an embodiment, a semiconductor wafer is provided that includes a plurality of component positions with scribe line regions located at least one of adjacent to and between the component positions. The component positions include an active device structure. An auxiliary structure is positioned in one or more of the scribe line regions. The auxiliary structure is electrically coupled to an auxiliary contact pad which includes tungsten. The auxiliary structure does not interact with or affect the active device structure in the component positions.

Semiconductor wafer having an auxiliary structure positioned in a scribe line region, semiconductor chip and method of fabricating a semiconductor wafer

A semiconductor device includes a semiconductor die having a vertical transistor device with a source electrode, a drain electrode and a gate electrode, the semiconductor die having a first surface and a second surface opposing the first surface. A first metallization structure is located on the first surface and includes at least one source pad coupled to the source electrode, at least one drain pad coupled to the drain electrode and at least one gate pad coupled to the gate electrode, A second metallization structure is electrically insulated from the semiconductor die by the electrically insulating layer.

Semiconductor device

In some embodiments, a semiconductor device includes a semiconductor die including a vertical transistor device having a source electrode, a drain electrode and a gate electrode, the semiconductor die having a first surface and a metallization structure. The metallization structure includes a first conductive layer above the first surface, a first insulating layer above the first conductive layer, a second conductive layer above the first insulating layer, a second insulating layer above the second conductive layer and a third conductive layer above the second insulting layer. The third conductive layer includes at least one source pad electrically coupled to the source electrode, at least one drain pad electrically coupled to the drain electrode and at least one gate pad electrically coupled to the gate electrode.

Semiconductor device having a metallization structure

A transistor device includes field plate contacts that electrically connect a final metallization layer to field electrodes in underlying trenches, and mesa contacts that electrically connect the final metallization layer to semiconductor mesas confined by the trenches. Each field plate contact is divided into field plate contact segments that are separated from one another. Each mesa contact is divided into mesa contact segments that are separated from one another. In a first area adjacent to an end of the trenches, a first line that runs perpendicular to the trenches intersects a first field plate contact segment of the field plate contacts and a first mesa contact segment of the mesa contacts. In a second area spaced inward from the first area, a second line that runs perpendicular to the trenches intersects a second field plate contact segment of the field plate contacts and a second mesa contact segment of the mesa contacts.

Contact structure for transistor devices

A semiconductor device is described. The semiconductor device includes: a semiconductor substrate; an electrode structure on or in the semiconductor substrate, the electrode structure including an electrode and an insulating material that separates the electrode from the semiconductor substrate; and a strain-inducing material embedded in the electrode. The electrode structure adjoins a region of the semiconductor substrate through which current flows in a first direction during operation of the semiconductor device. The electrode is under either tensile or compressive stress in the first direction. The strain-inducing material either enhances or at least partly counteracts the stress of the electrode in the first direction. Methods of producing the semiconductor device are also described.

Power semiconductor device having a strain-inducing material embedded in an electrode

A semiconductor wafer has a semiconductor body, an insulation layer on the semiconductor body, a scribeline region designated to be subjected to a wafer separation processing stage, and an optically detectable reference feature laterally spaced inward from the scribeline region and configured to serve as a reference position during the wafer separation processing stage. A corresponding method of processing the semiconductor wafer, a power semiconductor die and a semiconductor wafer separation apparatus are also described.

Optically detectable reference feature for processing a semiconductor wafer

A semiconductor device includes a gate structure extending from a first surface of a semiconductor portion into a mesa section between neighboring field electrode structures and an alignment layer formed on the first surface. The alignment layer includes mask pits formed in the alignment layer in a vertical projection of the field electrode structures. Sidewalls of the mask pits have a smaller tilt angle with respect to the first surface than sidewalls of the field electrode structures. The gate structure is in the vertical projection of a gap between neighboring mask pits.

Semiconductor device having an alignment layer with mask pits

The application relates to a semiconductor die having a semiconductor body including an active region, an insulation layer on the semiconductor body, and a sodium stopper formed in the insulation layer. The sodium stopper is arranged in an insulation layer groove which intersects the insulation layer vertically and extends around the active region. The sodium stopper is formed of a tungsten material filling the insulation layer groove.

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Villach, Austria

Oliver Blank