Globalfoundries Inc.

Infineon Technologies Ag

Advanced Micro Devices Corporation

International Business Machines Corporation

Oliver Aubel

Frank Feustel

Thomas Werner

Heinrich Koerner

Andreas Kurz

Martina Hommel

Jens Poppe

Wolfgang Hasse

Timothy Dooling Sullivan

Tom C Lee

Alvin Wayne Strong

Roman Boschke

Joerg Hohage

Axel Preusse

Deborah M Massey

Travis S Merrill

Georg Talut

Holger Pagel

Torsten Schmidt

Pascal Limbecker

Stanley W Polchlopek

Christian Hennesthal

A semiconductor wafer is provided including a plurality of dies, each of the plurality of dies including a plurality of semiconductor devices, a plurality of die seals, each of the plurality of die seals being formed at a perimeter of one of the plurality of dies, and a plurality of electrically conductive links, each of the plurality of conductive links connecting one of the plurality of die seals with another one of the plurality of die seals.

Wafer with improved plating current distribution

An explanation is given of, inter alia, methods in which the barrier material is removed at a via bottom or at a via top area by long-term heat treatment. Concurrently or alternatively, interconnects are coated with barrier material in a simple and uncomplicated manner by means of the long-term heat treatment.

Long-term heat treated integrated circuit arrangements and methods for producing the same

A semiconductor structure includes a semiconductor substrate, one or more interconnect layers provided over the substrate and a circuit. The circuit includes a plurality of circuit elements formed at the substrate and a plurality of electrical connections provided in the one or more interconnect layers. A die seal is provided in the one or more interconnect layers. A die seal leakage detection material is arranged in the one or more interconnect layers between the die seal and the plurality of electrical connections. The die seal provides a protection of the die seal leakage detection material from moisture if the die seal is intact. The die seal leakage detection material is adapted for providing a detectable modification of the circuit after an exposure of the die seal leakage detection material to moisture.

Semiconductor structure including a die seal leakage detection material, method for the formation thereof and method including a test of a semiconductor structure

The present disclosure relates to a semiconductor structure including a plurality of connecting lines arranged on a plurality of vertical levels, the plurality of connecting lines including at least a first connecting line arranged in a first vertical level and a second connecting line arranged in a second vertical level, different from the first vertical level, and a breakdown prevention layer placed in at least part of the vertical space separating the first connecting line from the second connecting line.

Vertical breakdown protection layer

Metal fuses in semiconductor devices may be formed on the basis of additional mechanisms for obtaining superior electromigration in the fuse bodies. To this end, the compressive stress caused by the current-induced metal diffusion may be restricted or reduced in the fuse body, for instance, by providing a stress buffer region and/or by providing a dedicated metal agglomeration region. The concept may be applied to the metallization system and may also be used in the device level, when fabricating the metal fuse in combination with high-k metal gate electrode structures.

Semiconductor device comprising metal-based eFuses of enhanced programming efficiency by enhancing metal agglomeration and/or voiding

Long-term heat-treated integrated circuit arrangements and methods for producing the same

In a test structure for determining dielectric breakdown events of a metallization system of semiconductor devices, a built-in compliance functionality may allow reliable switching off of the test voltage prior to causing high leakage currents, which may conventionally result in significant damage. Consequently, further failure analysis may be possible after the occurrence of a dielectric breakdown event.

Built-in compliance in test structures for leakage and dielectric breakdown of dielectric materials of metallization systems of semiconductor devices

In sophisticated integrated circuits, an electronic fuse may be formed such that an increased sensitivity to electromigration may be accomplished by including at least one region of increased current density. This may be accomplished by forming a corresponding fuse region as a non-linear configuration, wherein at corresponding connection portions of linear segments, the desired enhanced current crowding may occur during the application of the programming voltage. Hence, increased reliability and more space-efficient layout of the electronic fuses may be accomplished.

Semiconductor device comprising eFUSES of enhanced programming efficiency

A unified test structure which is applicable for all levels of a semiconductor device including a current path chain having a first half chain and a second half chain, wherein each half chain comprises lower metallization segments, upper metallization segments, an insulating layer between the lower metallization segments and the upper metallization segments, and connection segments. Each of the connection segments is electrically connected to a contact region of one of the lower metallization segments and to a contact region of one of the upper metallization segments to thereby electrically connect the respective lower metallization segment and the respective upper metallization segment, and the first half chain and the second half chain are of different configuration.

Unified test structure for stress migration tests

During the formation of complex metallization systems, a conductive cap layer may be formed on a copper-containing metal region in order to enhance the electromigration behavior without negatively affecting the overall conductivity. At the same time, a thermo chemical treatment may be performed to provide superior surface conditions of the sensitive dielectric material and also to suppress carbon depletion, which may conventionally result in a significant variability of material characteristics of sensitive ULK materials.

Providing superior electromigration performance and reducing deterioration of sensitive low-k dielectrics in metallization systems of semiconductor devices

Methods, systems and program products are disclosed for performing a stress test of a line in an integrated circuit (IC) chip. One embodiment of the method includes: applying a constant current Ito the line; and stress testing the line while applying the constant current Isuch that the constant current Iis not altered by a resistance change due to an onset of electromigration.

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Dresden, Germany

Oliver Aubel