Freescale Semiconductor,inc.

Motorola Corporation

University of Rochester

Olin L Hartin

Radu Mircea Secareanu

Suman K Banerjee

Bruce McRae Green

Charles E Weitzel

Qiang Li

Ellen Y Lan

Julio C Costa

Hsin-Hua P Li

Matthias Passlack

Lianjun Liu

Jonathan K Abrokwah

Jay Paul John

Karen Elizabeth Moore

Ernest Schirmann

Marino J Martinez

Walter Parmon

Lawrence Scott Klingbeil

Neil T Tracht

Elizabeth C Glass

Marcus R Ray

Jon T Adams

Craig Jasper

Philip Li

Mariam G Sadaka

Chun-Li Liu

Paige M Holm

Vishal P Trivedi

Jenn-Hwa Huang

James Albert Kirchgessner

Eby G Friedman

Thuy B Dao

Enrique Ferrer

Nicholas W Medendorp

Colby Greg Rampley

Monte Gene Miller

Michael J Zunino

Sateh Jalaleddine

Randy D Redd

Sandra J Wipf

Ngai Ming Lau

Alain C Duvallet

Mikhail Popovich

Paul A Fisher

H Philip Li

Wendy L Valentine

Emre Salman

Alain C Duvalley

A low leakage current switch device () is provided which includes a GaN-on-Si substrate (-) covered by a passivation surface layer () in which a T-gate electrode with sidewall extensions () is formed and coated with a conformal passivation layer () so that the T-gate electrode sidewall extensions are spaced apart from the underlying passivation surface layer () by the conformal passivation layer ().

High speed gallium nitride transistor devices

An integrated circuit includes a p-well block region having a low doping concentration formed in a region of a substrate for providing noise isolation between a first circuit block and a second circuit block. The integrated circuit further includes a guard region and a grounded, highly doped region for providing additional noise isolation.

Noise isolation between circuit blocks in an integrated circuit chip

An electronic apparatus includes a semiconductor substrate, a circuit block disposed in and supported by the semiconductor substrate and comprising an inductor, and a discontinuous noise isolation guard ring surrounding the circuit block. The discontinuous noise isolation guard ring includes a metal ring supported by the semiconductor substrate and a ring-shaped region disposed in the semiconductor substrate, having a dopant concentration level, and electrically coupled to the metal ring, to inhibit noise in the semiconductor substrate from reaching the circuit. The metal ring has a first gap and the ring-shaped region has a second gap.

Integrated circuit chip with discontinuous guard ring

Embodiments of antennas and radio frequency (RF) modules include a substrate, a first antenna arm coupled to the substrate, and a first conductive structure between a distal end of the first antenna arm and a bottom surface of the substrate. An embodiment of a system includes a first substrate, a first conductive structure on a top surface of the first substrate, and an antenna coupled to the top surface of the first substrate. The antenna includes a second substrate, a first antenna arm coupled to the second substrate, and a second conductive structure having a proximal end and a distal end. The proximal end of the second conductive structure is coupled to a distal end of the first antenna arm, and the distal end of the second conductive structure extends to a bottom surface of the second substrate and is coupled to the first conductive structure on the first substrate.

Extendable-arm antennas, and modules and systems in which they are incorporated

An embodiment of an antenna includes a radiation frame and a planar inverted-F antenna (PIFA). The radiation frame has a frame shape that defines a central opening. The PIFA includes an antenna arm, a feed arm, and a shorting arm. A distal end of the shorting arm is conductively coupled with the radiation frame. The antenna may be coupled to a substrate of an RF module. The RF module may be included in a system that also includes a non-RF component that produces a signal for transmission. In such a system, the RF module is configured to receive the signal, convert the signal to an RF signal, and radiate the RF signal over an air interface.

Planar inverted-F antennas, and modules and systems in which they are incorporated

A balanced-unbalanced (balun) signal transformer includes an unbalanced port, a balanced port coupled to the unbalanced port, the balanced port comprising a first terminal and a second terminal, a first capacitor coupled to the first terminal, a first inductor coupled to ground and the first capacitor, a second capacitor coupled to the second terminal, and a second inductor coupled to ground and the second capacitor. The transformer may also include a third capacitor coupled to a terminal of the unbalanced port; and a third inductor coupled to the third capacitor and the third terminal.

Balun signal transformer and method of forming

Apparatus and a method are provided for reducing noise in mixed-signal and digital circuits. One apparatus () includes a metal-oxide-semiconductor field-effect transistor (MOSFET) (). MOSFET () includes a doped substrate () with a source formed proximate a substrate tie () and a substrate tie () adjacent substrate (). A ground rail () is coupled to the source and substrate tie (), and a ground rail () is coupled to substrate tie (). Ground rails () and () are configured to be coupled to different ground networks (and). One method includes producing a model of a semiconductor device including a standard semiconductor cell (). The semiconductor cell is identified as a noise-sensitive or a noise-producing semiconductor cell (), and the semiconductor cell is replaced with a corresponding noise-aware semiconductor cell ().

Apparatus and method for reducing noise in mixed-signal circuits and digital circuits

An improved varactor diode () is obtained by providing a substrate () having a first surface (), in which are formed a P+ region () proximate the first surface (), a first N region () located beneath the P+ region (), an N well region () located beneath the first N region () and a first P counter-doped region () located between the first N region () and the N well region (), thereby forming an P+NPN structure for the varactor diode. In some embodiments, a second P-type counter-doped region () is provided within the N-well region () so as to reduce the N doping concentration within the N well region () but without creating a further PN junction therein. The net doping profile () provides varactor diodes () having a larger tuning ratio than varactors () without such counter-doped regions. By interchanging N and P regions an N+PNP varactor is obtained.

Counter-doped varactor structure and method

Apparatus are provided for routing interconnects of a dual-gate electronic device operating in a differential configuration. An electronic apparatus formed on a substrate is provided comprising a first interconnect () configured to couple to a first region of the substrate, a first gate () coupled to the first interconnect and configured to receive a first differential input, a second interconnect () parallel to the first interconnect and configured to couple to a second region of the substrate, and a second gate () coupled to the second interconnect and configured to receive a second differential input. The first gate is parallel to the first interconnect, and the second gate is parallel to the second interconnect.

Electronic apparatus interconnect routing

An electronic assembly includes a substrate (), a balun transformer () formed on the substrate () and including a first winding () and a second winding (), each having respective first and second ends, and a reaction circuit component () formed on the substrate () and electrically coupled to the second winding () between the first and second ends thereof. The balun transformer () and the reaction circuit component () jointly form a harmonically suppressed balun transformer having a fundamental frequency, and the reaction circuit component () is tuned such that the harmonically suppressed balun transformer resonates at a selected harmonic of the fundamental frequency.

Balun transformer with improved harmonic suppression

Method and apparatus are provided for routing interconnects of a dual-gate electronic device operating in a differential configuration. An electronic apparatus formed on a substrate is provided comprising a first interconnect () configured to couple to a first region of the substrate, a first gate () coupled to the first interconnect and configured to receive a first differential input, a second interconnect () parallel to the first interconnect and configured to couple to a second region of the substrate, and a second gate () coupled to the second interconnect and configured to receive a second differential input. The first gate is parallel to the first interconnect, and the second gate is parallel to the second interconnect.

Electronic apparatus interconnect routing and interconnect routing method for minimizing parasitic resistance

Flip-chip electronic devices () employ bumps () for coupling to an external substrate. Device cells () and bumps () are preferably arranged in clusters () where four bumps () substantially surround each device cell () or form a cross with the device cell () at the intersection of the cross. The bumps () are desirably spaced apart by the minimum allowable bump () pitch (L). Typically, each device cell () contains one or more active device regions () depending on the overall function. Complex devices () are formed by an X-Y array of the clusters (), where adjacent clusters () may share bumps () and/or device cells (). In a preferred embodiment, the bumps () form the outer perimeter () of the device (). The maximum device temperature and overall noise is reduced.

Electronic device with connection bumps

An integrated circuit includes a p-well block region having a high resistivity due to low doping concentration formed in a region of a substrate for providing noise isolation between a first circuit block and a second circuit block. The integrated circuit further includes a guard region formed surrounding the p-well block region for providing noise isolation between the first circuit block and the second circuit block.

A system-on-chip or other circuit has an on-chip noise-free ground which is added to divert ground noise from the sensitive nodes. An on-chip decoupling capacitor, tuned in resonance with the parasitic inductance of the interconnects, can be provided to add an additional low impedance ground path.

Method and apparatus to reduce noise fluctuation in on-chip power distribution networks

Growing community of inventors

Chandler, AZ, United States of America

Olin L Hartin