Freescale Semiconductor,inc.

Olga R Lu

Lawrence F Childs

Craig D Gunderson

James David Burnett

Thomas W Liston

Glenn E Starnes

Mark W Jetton

A multi-port memory device having a storage node, a precharge node, a first, second, third, and fourth transistor, and a control module. The first transistor includes a current electrode connected to the storage node, another current electrode connected to a first bit line, and a gate connected to a first wordline. The second transistor includes a current electrode connected to the storage node, another current electrode connected to a second bit line, and a gate connected to a second wordline. The third transistor includes a current electrode connected to the reference node, another current electrode connected to the first bit line, and a gate. The fourth transistor includes a current electrode connected to the precharge node, another current electrode connected to the second bit line, and a gate. The control module deactivates the fourth transistor in response to a dummy access of the first storage module at the second transistor.

Dual port memory device

A memory has an array of memory cells, column logic, a write driver, a voltage detector, and a bootstrap circuit. The array of memory cells is coupled to pairs of bit lines and word lines. The column logic is coupled to the array and is for coupling a selected pair of bit lines to a pair of data lines. The write driver is coupled to the pair of data lines. The voltage detector provides an initiate boost signal when a voltage of a first data line of the pair of data lines drops below a first level during the writing of the pair of data lines by the write driver. The bootstrap circuit reduces the voltage of the first data line in response to the boost enable signal. This is particularly beneficial when the number of memory cells on a bit line can vary significantly as in a compiler.

Memory having self-timed bit line boost circuit and method therefor

A memory having at least one memory array block, the at least one memory array block comprising N wordlines, wherein N is greater than one, is provided. The memory comprises a plurality of sense amplifiers coupled to the at least one memory array block. The memory further comprises at least one dummy bitline, wherein the at least one dummy bitline comprises M dummy bitcells, wherein M is equal to N. The memory further comprises a timing circuit coupled to the at least one dummy bitline, wherein the timing circuit comprises at least one stack of pull-down transistors coupled to a sense circuit for generating a latch control output signal used for timing control of memory accesses. Timing control may include generating a sense trigger signal to enable the plurality of sense amplifiers for read operations and/or generating a local reset signal for terminating memory accesses, such as disabling the plurality of write drivers for write operations.

Memory having a dummy bitline for timing control

A memory circuit has a memory array with a first line of memory cells, a second line of memory cells, a first power supply terminal, a first capacitance structure, a first power supply line coupled to the first line of memory cells; and a second power supply line coupled to the second line of memory cells. For the case where the second line of memory cells is selected for writing, a switching circuit couples the power supply terminal to the first power supply line, decouples the first power supply line from the second line of memory cells, and couples the second power supply line to the first capacitance structure. The result is a reduction in power supply voltage to the selected line of memory cells by charge sharing with the capacitance structure. This provides more margin in the write operation on a cell in the selected line of memory cells.

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Austin, TX, United States of America

Olga R Lu