Freescale Semiconductor,inc.

Nxp Usa, Inc.

Oleksandr Sakada

Florian Bogenberger

Vladimir Litovtchenko

Anthony M Reipold

A method is provided for detecting a race condition of a parallel task when accessing a shared resource in a multi-core processing system. The method requires that a core requires only a read access to the data set of another core, thereby ensuring better decoupling of the tasks. In an initialisation phase, initial values of global variables are assigned, in an activation phase, each core determines if the other core has written new values to the variables and if so, detects a race condition. Initial values are restored for each variable in a deactivation phase.

Method and device for detecting a race condition and a computer program product

A method for detecting a race condition, comprising storing a seed value to a first global variable D; detecting a race condition when the second global variable A does not equal a first predefined value Vwherein the second global variable A was set to the first predefined value Vat the initiation event prior to storing the seed value; storing a second predefined value Vto the second global variable A; detecting a race condition when the first global variable D does not equal the seed value; accessing a shared resource; and storing the first predefined variable Vto the second global variable A.

Method and device for detecting a race condition

A processing resource apparatus comprises a reference processing module comprising a set of reference stateful elements and a target processing module comprising a set of target stateful elements. A scan chain having a first mode for supporting manufacture testing is also provided, the scan chain being arranged to couple the reference processing module to the target processing module. The scan chain also has a second mode capable of synchronizing the set of target stateful elements with the set of reference stateful elements in response to a synchronization signal.

Synchronization of stateful elements in a processing resource using a scan chain

A semiconductor device comprises processing logic arranged to execute program instructions. The semiconductor device further comprises signature generation logic arranged to receive at least one value from at least one internal location of the semiconductor device, and to generate a current signature value, based on the at least one received value. Validation logic is arranged to validate the current signature value generated by the signature generation logic. The processing logic is further arranged, upon execution of a signature validation instruction, to enable the validation of the current signature value provided by the validation logic.

Semiconductor device and method for validating a state thereof

A data processing control unit for controlling two or more data processing operations SMI,SMI. The data processing control unit may include a control memory in control data may be stored which represents information about access to a main memory by the two or more data processing operations. A control data controller may be connected to the control memory. The control data controller may include a control data controller input or receiving an access request from one or more of the data processing operations. The control data controller may modify the data in the control memory upon receiving the access request. A process controller may be connected to the control memory. The process controller may control at least a part of the data processing operations SMI.SMIbased on a comparison of data in the control memory with a criterion. The process controller may include a process controller input for receiving the access request; and a process controller output for outputting a process control signal based on the comparison.

Data processing control unit for controlling multiple data processing operations

A system for testing a logic circuit which has two or more test routine modules. Each module contains a set of instructions which is executable by (a part of) the logic circuit. The set forms a test routine for performing a self-test by the part of the logic circuit. The self-test includes the part of the logic circuit testing itself for faulty behavior, and the part of the logic circuit determining a self-test result of the testing. The system includes a test module which can execute a test application which subjects the logic circuit to a test by performing the self-test on at least a part of the logic circuit by causes the part of the logic circuit to execute a selected test routine, and determining, by the test module, an overall test result at least based on a performed self-tests. The test module includes a control output interface for activates the execution of the a selected test routine. A second test module input interface can receive the self-test result from a selected test routine. At a test module output interface the overall test result may be outputted. The test routine includes instructions for outputting, by the part of the logic circuit, data to a test routine output interface which is not connected to the second test module input interface, for outputting information about the self-test result by the test routines without passing the information through the test module.

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Munich, Germany

Oleksandr Sakada