Skyworks Solutions, Inc.

Rfaxis, Inc.

Stmicroelectronics Gmbh

Berex Corporation

Mobix Labs, Inc.

Stmicroelectronics S.r.l.

Skyworks Soultions, Inc.

Octotech, Inc.

Oleksandr Gorbachov

Lisette L Zhang

Lothar Musiol

Huan Zhao

Floyd Ashbaugh

Qiang Li

Yongxi Qian

Aydin Seyedi

Ziming He

Giuseppe Avellone

Yang Liu

Salvatore Scaccianoce

Antonino Calcagno

Parham Khajeh Hesamaddin

Ping Peng

Xu Shao

Lothar Johannes Musiol

Okjune Jeon

Taewon Jung

Hyon Su Han

Stephen Milkovits

Raymond Biagan

An antenna array module includes two or more antenna elements arranged in an array, each of the two or more antenna elements formed as a respective integrated passive device (IPD), and a multi-layer printed circuit board (PCB) including one or more metal layers forming one or more feed lines of the antenna elements. The antenna array module may include a radio frequency (RF) front end integrated circuit disposed on an opposite side of the multi-layer PCB from the two or more antenna elements. One or more signal output pins of the RF front end integrated circuit may be connected to the one or more feed lines. The antenna array module may include conductive contacts external to the multi-layer PCB for routing input signals through the multi-layer PCB to one or more signal input pins of the RF front end integrated circuit.

Low-cost, IPD and laminate based antenna array module

A radio frequency front end circuit for a multimode transceiver has a first operating mode transmit input port, a second operating mode transmit input/receive output port, and a hybrid first and second operating mode receive output port. A first switch network has one or more switch elements together selectively connecting the first operating mode transmit input port, the second operating mode transmit input/receive output port, and the hybrid first and second operating mode receive output port to a coexistence filter first port. A second switch network has one or more switch elements that together selectively connect a coexistence filter second port to an antenna port.

Multi-mode WiFi bluetooth RF front-ends

A metal oxide semiconductor field effect transistor preferably fabricated with a silicon-on-insulator process has a first semiconductor region and a second semiconductor region in a spaced relationship thereto A body structure is defined by a channel segment between the first semiconductor region and the second semiconductor region, and a first extension segment structurally contiguous with the channel segment. A shallow trench isolation structure surrounds the first semiconductor region, the second semiconductor region, and the body structure, with a first extension interface being defined between the shallow trench isolation structure and the first extension segment of the body structure to reduce leakage current flowing from the second semiconductor region to the first semiconductor region through a parasitic path of the body structure.

Low noise amplifier transistors with decreased noise figure and leakage in silicon-on-insulator technology

A dual-band cross-polarized antenna includes first and second metal layers defining respective first and second driven patches configured to radiate at different frequencies, first and second feed pins connecting a first feed line to the first driven patch at respective first and second feed points thereof associated with orthogonal polarizations, and third and fourth feed pins connecting a second feed line to the second driven patch at first and second feed points thereof associated with orthogonal polarizations. The third feed pin extends through a first hole in the first driven patch to capacitively couple the third feed pin to the first driven patch. The fourth feed pin extends through a second hole in the first driven patch to capacitively couple the fourth feed pin to the first driven patch. Two or more antenna elements are arranged as a phased array antenna and packaged as an antenna module.

Dual-band cross-polarized 5G mm-wave phased array antenna

A resonant switch with a first port and a second port has a capacitor connected thereto. A triple inductor network has a center inductor connected to the first port and the second port, and first and second peripheral inductors each electromagnetically coupled thereto. In a deactivated state, the center inductor and the capacitor define a parallel resonance at a predefined operating frequency range, and in an activated state, insertion loss associated with the center inductor is substantially minimized to metallic trace loss attributable thereto.

Low-loss mm-wave CMOS resonant switch

An RF receiver circuit configuration and design is limited by conditions and frequencies to simultaneously provide steady state low-noise signal amplification, frequency down-conversion, and image signal rejection. The RF receiver circuit may be implemented as one of a CMOS single chip device or as part of an integrated system of CMOS components.

Receiver architectures with parametric circuits

An ultra-high coupling factor transformer has a plurality of conductive layers, a primary winding inductor, and a secondary winding inductor. The primary winding inductor is defined by a plurality of turns and disposed on a first one of the plurality of conductive layers and extends to a second one of the plurality of conductive layers. The secondary winding inductor is defined by a plurality of turns and disposed on the first one of the plurality of conductive layers and extends to the second one of the plurality of conductive layers. The primary winding is vertically and horizontally cross coupled with the secondary winding inductor, and defines a mutual coupling inductance from surrounding directions.

Ultra-high coupling factor monolithic transformers for integrated differential radio frequency amplifiers in system-on-chip devices

A phase shifter with a first port and a second port has a triple inductor network with a center inductor connected to the first port and the second port, and first and second peripheral inductors each electromagnetically coupled to the center inductor. A resistance switch network that is connected to the first and second peripheral inductors. The resistance switch network is selectively activatable to set a first state defined at least by a first resistance in a series circuit with the first and second peripheral inductors, a second state defined at least by a second resistance in the series circuit, and a third state defined at least by a third resistance in the series circuit. A transmission signal from the first port to the second port is shifted in phase by a prescribed angle corresponding to forward transmission coefficients for the first state, second state, and third state.

Low-loss bi-directional passive LSB phase shifter in mm-wave CMOS

An integrated circuit architecture and circuitry is defined by a die structure with a plurality of exposed conductive pads arranged in a grid of rows and columns. The die structure has a first operating frequency region with a first transmit and receive chain, and a second operating frequency region with a second transmit chain and a second receive chain. There is a shared region of the die structure defined by an overlapping segment of the first operating frequency region and the second operating frequency region with a shared power supply input conductive pad connected to the first transmit chain, the second transmit chain, the first receive chain, and the second receive chain, and a shared power detection output conductive pad connected to the first transmit chain and the second transmit chain.

Multiple band multiple mode transceiver front end flip-chip architecture and circuitry with integrated power amplifiers

A radio frequency (RF) power amplifier (PA) for amplifying an RF signal between a source node and an output node, the RF PA including a silicon substrate with a complementary metal oxide semiconductor (CMOS) N-type transistor with a source region and a drain region fabricated therein. The source region includes the source node of the RF PA and the drain region includes the output node of the RF PA. The RF PA includes a planar resistor fabricated on the surface of the silicon substrate proximal to the drain region of the N-type transistor, wherein the resistor provides a thermal source for heating the RF PA; and a control circuit providing thermal heating to the RF PA by providing power to the planar resistor during RF signal bursts wherein the added thermal heating compensates transient heating within the transistor and results in a linear power amplification operation.

Control circuit for a radio frequency power amplifier

A zero insertion loss directional coupler includes an input port, an antenna port, an isolation port, and a detect port. The coupler has a first signal trace, a second signal trace, and an inductive winding. The first signal trace is on one of two layers and is connected to the input port and the antenna port, while the inductive winding is on another one of the two layers. A first terminal of the inductive winding is connected to the isolation port. A first terminal of the second signal trace is connected to the detect port and a second terminal of the second signal trace is connected to a second terminal of the inductive winding.

Zero insertion loss directional coupler for wireless transceivers with integrated power amplifiers

An RF power limiter and ESD protection circuit has a set of two CMOS FETs each configured to perform a diode function with a defined forward voltage and arranged in an anti-parallel configuration and coupled between the input terminal and the ground terminal. When an RF signal is applied symmetrically to the input terminal and ground terminal it becomes symmetrically attenuated when the signal level exceeds the defined forward voltage of the diode configured CMOS FETs. In the ESD protection mode one of the CMOS FETs acts as a grounded gate NMOS transistor with SCR action to provide for mitigation of voltage and current over-stress of transistors utilized in RF transceiver circuits. Generally, the circuit architectures allow input power levels to be limited to an extent that reliable operation can be maintained.

CMOS RF power limiter and ESD protection circuits

An RF receiver circuit configuration and design limited by conditions and frequencies to simultaneously provide steady state low-noise signal amplification, frequency down-conversion and image signal rejection. The invention provides combined circuits of an RF transceiver architecture that measure antenna reflected power relative to forward power using the error amplifier signal to adjust the gain of the variable gain amplifier in order to compensate for the mismatch between forward reflected power and forward power at the antenna in order to achieve constant radiated power. The RF receiver circuit may be implemented as one of a CMOS single chip device or as part of an integrated system of CMOS components.

RF power amplifier circuits for constant radiated power and enhanced antenna mismatch sensitivity

A radio frequency low noise amplifier circuit with a receive signal input, a receive signal output, and a voltage source include a low noise amplifier and a coupled inductor circuit with a primary inductive chain connected to the output of the low noise amplifier and to the voltage source. The coupled inductor circuit further includes a secondary inductive chain with a first inductor electromagnetically coupled to the primary inductive chain, and a second inductor in series with the first inductor and magnetically coupled to the primary inductive chain. The second inductor is connected to a feedback node of the low noise amplifier. There is an output matching network connected to the first inductor of the secondary inductive chain and to the receive signal output.

Growing community of inventors

Irvine, CA, United States of America

Oleksandr Gorbachov