Seh America, Inc.

Oleg V Kononchuk

Sergei V Koveshnikov

Zbigniew J Radzimski

Gerald R Dietze

Neil A Weaver

Mark R Boydston

Akihiko Tamura

Scott Matthew Kirkland

Stephen L Martin

George Preece

A method of growing epitaxial semiconductor layers with reduced crystallographic defects. The method includes etching the wafer surface and then growing an initial portion of the epitaxial layer under conditions of relatively high temperature and low source gas flow to heal defects in or on the surface of the substrate. Subsequently, the remainder of the epitaxial layer is grown under high growth rate conditions resulting from high source gas flow. The initial portion of the epitaxial layer acts as a low-defect seed layer by preventing defects in the surface of the substrate from propagating into the remainder of the epitaxial layer. However, the relatively high source gas flow permits the remainder epitaxial layer to be grown at a faster rate than the initial portion of the epitaxial layer.

Growth of epitaxial semiconductor material with improved crystallographic properties

An improved method of obtaining a wafer exhibiting high resistivity and high gettering effect while preventing the reduction of resistivity due to the generation of oxygen donors provided by: a) using the CZ method to grow a silicon single crystal ingot having a resistivity of 100 &OHgr;&middot;cm or more, preferably 1000 &OHgr;&middot;cm, and an initial interstitial oxygen concentration of 10 to 40 ppma while doping the crystal with an electrically inactive material such as nitrogen, carbon, or tin, b) processing the ingot into a wafer, and c) subjecting the wafer to an oxygen precipitation heat treatment whereby the residual interstitial oxygen content in the wafer is reduced to about 8 ppma or less.

High resistivity silicon wafer having electrically inactive dopant and method of producing same

A method of obtaining a wafer exhibiting high resistivity and high gettering effect while preventing the reduction of resistivity due to the generation of oxygen donors, and while further minimizing in-grown defects is provided by: a) using the CZ method to grow a silicon single crystal ingot having a resistivity of 100 &OHgr;&middot;cm or more, preferably 1000 &OHgr;&middot;cm, and an initial interstitial oxygen concentration of 10 to 40 ppma with a v/G ratio of from about 1&times;10 cm /s&middot;K to about 5&times;10 cm /s&middot;K, b) processing the ingot into a wafer, and c) subjecting the wafer to an oxygen precipitation heat treatment whereby the residual interstitial oxygen content in the wafer is reduced to about 8 ppma or less.

High resistivity silicon wafer produced by a controlled pull rate czochralski method

A high resistivity wafer which does not exhibit diminishing resistivity after device installation and method of making the high resistivity wafer comprising a) using the CZ method to grow a silicon single crystal ingot with a resistivity of 100 &OHgr;&middot;cm or more, preferably 1000 &OHgr;&middot;cm or more, and an initial interstitial oxygen concentration of 10 to 40 ppma, b) processing the ingot into a wafer, c) determining the total amount of heat treatment required to reduce the interstitial oxygen content of the wafer to about 8 ppma or less, d) determining the amount of heat treatment which will take place during the device fabrication process after wafer fabrication, e) subjecting the wafer to a partial oxygen precipitation heat treatment equivalent to the total amount of heat treatment, less the amount of heat treatment that will occur during device fabrication.

Method of producing a high resistivity silicon wafer utilizing heat treatment that occurs during device fabrication

A silicon wafer having a thick, high-resistivity epitaxially grown layer and a method of depositing a thick, high-resistivity epitaxial layer upon a silicon substrate, such method accomplished by: a) providing a silicon wafer substrate and b) depositing a substantially oxygen free, high-resistivity epitaxial layer, with a thickness of at least 50 &mgr;m, upon the surface of the silicon wafer. The silicon wafer substrate may then, optionally, be removed from the epitaxial layer.

High resistivity silicon wafer with thick epitaxial layer and method of producing same

An improved method of obtaining a wafer exhibiting high resistivity while preventing the reduction of resistivity due to the generation of oxygen donors provided by: a) using the CZ method to grow a silicon single crystal ingot in the presence of a magnetic field, such crystal having a resistivity of 100 &OHgr;&middot;cm or more and an initial interstitial oxygen concentration of 5 to 10 ppma and b) processing the ingot into a wafer.

High resistivity silicon wafer and method of producing same using the magnetic field Czochralski method

A process for forming an epitaxial layer on a semiconductor wafer substrate is provided. The process comprises providing a semiconductor wafer substrate and an area for forming an epitaxial layer on said semiconductor wafer substrate. The formation area consists essentially of an epitaxial layer process chamber. The semiconductor wafer substrate is introduced into the epitaxial layer process chamber and an epitaxial layer is formed on at least one surface of the semiconductor wafer substrate. Then, a chemical reagent is introduced into the epitaxial layer process chamber. The chemical reagent reacts with the epitaxial layer surface in situ to form an outer protective oxide layer.

In-situ post epitaxial treatment process

A method of growing epitaxial semiconductor layers with reduced crystallographic defects. The method includes growing a first epitaxial semiconductor layer on a semiconductor substrate under conditions of relatively high temperature and low source gas flow to heal defects in or on the surface of the substrate. Subsequently, a second epitaxial semiconductor layer is grown on the first layer under conditions of relatively low temperature and high source gas flow. The first epi layer acts as a low-defect seed layer by preventing defects in the surface of the substrate from propagating into the second epi layer. Optionally, a hydrogen chloride etch may be employed during a portion of the first epi layer growth to increase the efficacy of the first layer.

A process for demounting silicon wafers from a polishing plate is provided, wherein a polishing plate containing wafers is subjected to a fluid stream to separate the wafer from the polishing plate. The wafer then passes through a fluid stream to rinse the wafer. Finally, the wafer is placed in a cassette that is submerged in a dilute solution of hydroflouric acid and water, and waits in que for a standard cleaning process. By storing the wafer in the solution containing hydroflouric acid, metal precipitation on the surface of the wafer is prevented.

Method of demounting silicon wafers after polishing

A wire saw slicing apparatus capable of slicing a cylindrical workpiece into wafers having a flat shape with reduced bow and warp. The slicing apparatus includes a layer of parallel wires moving with reciprocating or continuous movement while a workpiece is advanced through the wires, while an abrasive containing slurry is supplied. The parallel wires are wound around wire guides, wherein the outer sleeve of the wire guide has a higher thermal coefficient of expansion, and the substructure of the wire guide has a lower thermal coefficient of expansion, with the substructure having flanges at the axial ends that restrict the outer sleeve from expanding axially.

Apparatus and method for reducing bow and warp in silicon wafers sliced by a wire saw

A low cost method of manufacturing a silicon substrate having both impurity gettering and protection against CMOS latch up. The method includes performing a low energy implant of a selected acceptor ion to form a low resistivity buried layer closely adjacent the front surface of a silicon wafer. A low energy silicon implant is also performed to create a plurality of gettering sites closely adjacent the front surface. Subsequently, an epitaxial silicon layer is grown on the front surface.

Low cost silicon substrate with impurity gettering and latch up protection and method of manufacture

A system and method for sorting semiconductor substrates based on substrate thickness. The invention includes weighing each semiconductor substrate to be sorted, and then calculating the thickness of each substrate from its mass, area and density. The system may be configured to automatically sort the substrates according to the weight-based thickness calculations.

System and method for wafer thickness sorting

A method of determining the thickness of a layer on a substrate where the layer is deposited during a semiconductor manufacturing process. The substrate is weighed a first time. The layer is deposited on the substrate and the substrate is weighed a second time. The thickness of the layer is calculated using the difference between the second weighing and the first weighing.

Method of determining the thickness of a layer on a silicon substrate

An improved method is provided for processing the backside of a wafer within an epitaxial reactor chamber, such as by etching the backside of the wafer or applying a back seal to the backside of the wafer. The backside of the wafer can therefore be processed within the reactor chamber and an epitaxial layer can then be deposited on the front side of the wafer without ever removing the wafer from the epitaxial reactor chamber. In one embodiment, the backside of the wafer is processed by applying a back seal layer to the backside of the wafer. The back seal layer can be applied by either passing a gas over the backside of the wafer or by setting the wafer upon a sacrificial wafer. In either instance, the gas or the sacrificial wafer reacts with the wafer to grow the back seal layer on the backside of the wafer. In another embodiment, the backside of the wafer is processed by etching the backside of the wafer, such as by passing a reactive gas over the backside of the wafer. Once the backside of the wafer has been processed, such as by applying a back seal layer or by etching the backside of the wafer, an epitaxial layer is deposited on the front side of the wafer without ever removing the wafer from the epitaxial reactor chamber, thereby reducing the cost and fabrication time of the resulting wafers.

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Brush Prairie, WA, United States of America

Oleg V Kononchuk