Newport Fab, LLC

Oleg Martynov

Edward J Preisler

Farnood Rezaie

William Krieger

A stress-reduced silicon photonics semiconductor wafer includes a silicon nitride layer on a backside of the wafer. At least one silicon nitride stress-reduction configuration is on a topside of the wafer. At least one silicon nitride photonics device is also on the topside of the wafer. A silicon photonics device can be situated in the wafer.

Stress-reduced silicon photonics semiconductor wafer

A method of integrating an optoelectronic device comprising a Pockels material, such as lithium niobate (LiNbO3), includes forming an optoelectronic device layer over a semiconductor layer. The optoelectronic device layer includes a patterned optoelectronic device segment in an interlayer dielectric. A window is etched in the interlayer dielectric using the patterned optoelectronic device segment as a sacrificial etch stop. The patterned optoelectronic device segment is removed in the window. The optoelectronic device comprising the Pockels material is formed in place of the removed patterned optoelectronic device segment. The optoelectronic device comprising the Pockels material may be formed from an optoelectronic chiplet.

Integration of optoelectronic devices comprising lithium niobate or other Pockels materials

A semiconductor structure includes a group IV substrate and a patterned group III-V device over the group IV substrate. A blanket dielectric layer is situated over the patterned group III-V device. A contact metal is situated within the blanket dielectric layer and an interconnect metal is situated over the blanket dielectric layer. The blanket dielectric layer can be substantially planar. The contact metal and the interconnect metal can be electrically connected to the patterned group III-V device. The patterned group III-V device can be optically and/or electrically connected to group IV devices in the group IV substrate.

Semiconductor structure having group III-V device on group IV substrate

There are disclosed herein various implementations of a silicon-on-insulator (SOI) die including a light emitting layer pedestal-aligned with a light receiving segment, as well as methods for fabricating such an SOI die. The SOT die includes a pedestal region of the SOI die having a pedestal including a thin top silicon segment, a buried oxide (BOX) segment, and a handle wafer segment. The SOI die also includes an integrated circuit (IC) region having a thin silicon waveguide that is aligned with the thin top silicon segment in the pedestal region. A light emitting layer is situated over the pedestal in the pedestal region, the light emitting layer being aligned with the light receiving segment to situated over the thin silicon waveguide in the IC region.

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Lebanon, NH, United States of America

Oleg Martynov