International Business Machines Corporation

Globalfoundries Inc.

Other

Infineon Technologies Ag

Ultratech, Inc.

Globalfoundries U.S. Inc.

Infineon Technologies North America Corp.

Oleg Gluschenkov

Alexander Reznicek

Shogo Mochizuki

Bruce Bennett Doris

Omer H Dokumaci

Dureseti Chidambarrao

Huilong Zhu

Veeraraghavan S Basker

Tenko Yamashita

Zuoguang Liu

Ruilong Xie

Jack Allan Mandelman

Hiroaki Niimi

Sanjay C Mehta

Dae-Gyu Park

Kangguo Cheng

Carl John Radens

Ping-Chuan Wang

Helmut Horst Tews

Rajarao Jammy

Takashi Ando

Chun-chen Yeh

Michael Patrick Chudzik

Haining S Yang

Ying Di Zhang

Cyril Cabral, Jr

Louis L Hsu

Chen Zhang

Julien Frougier

Soon-Cheon Seo

Haizhou Yin

Kern Rim

Injo Ok

Unoh Kwon

Chih-Chao Yang

Devendra K Sadana

Steven J Holmes

Rajiv V Joshi

Toshiharu Furukawa

Dechao Guo

Balasubramanian Pranatharthiharan

Judson Robert Holt

Heng Wu

Praneet Adusumilli

Ekmini Anuja De Silva

Hayden C Cranford, Jr

Yann Mignot

Ravikumar Ramachandran

Renee Tong Mo

Ahmet Serkan Ozcan

Rajasekhar Venigalla

Richard Anthony Conti

Lawrence Alfred Clevenger

Bahman Hekmatshoartabari

Ramachandra Divakaruni

Hemanth Jagannathan

Michael Rizzolo

Keith Kwong Hon Wong

Ruqiang Bao

Fee Li Lie

Oscar Van Der Straten

Andrew Mark Greene

Koichi Motoyama

Andrew Herbert Simon

Richard Paul Volant

Koji Watanabe

Siddarth A Krishnan

Meikei Ieong

Jochen C Beintner

Juntao Li

Effendi Leobandung

Junli Wang

Choonghyun Lee

Stephen W Bedell

Chung H Lam

Chanro Park

Nicolas J Loubet

Vijay Narayanan

Kevin K Chan

Zhenxing Bi

Zhijiong Luo

Christian Lavoie

Xiangdong Chen

Robert Russell Robison

Min Gyu Sung

Dominic Joseph Schepis

Matthew Earl Colburn

Martin Michael Frank

Su Chen Fan

Hanyi Ding

Nicholas Anthony Lanzillo

Brian Joseph Greene

Eduard Albert Cartier

Thomas W Dyer

Bomy A Chen

Joshua M Rubin

Eric R Miller

Gary Bela Bronner

Muthumanickam Sankarapandian

Anthony I Chou

A via connection layer for an electronic package and method for fabricating a via connection layer are provided. The via connection layer includes asymmetric via(s) formed in the via connection layer. The asymmetric via include a first sidewall with a first slope angle in a first direction and a second sidewall, where the second sidewall includes a second slope angle in the first direction.

Enhanced linerless vias

A semiconductor structure includes a first metallization layer having a first plurality of metal containing lines, and a second metallization layer located above the first metallization layer. The second metallization layer includes a second plurality of metal containing lines. A first group of the second plurality of metal containing lines is disposed within the first metallization layer. The first group of the second plurality of metal containing lines is isolated from the first metallization layer by a dielectric barrier layer.

Semiconductor structure with backside metallization layers

A microelectronic structure including a stacked transistor having a lower transistor and an upper transistor. A shared contact in contact with a lower source/drain of the first lower transistor and an upper source/drain of the upper transistor. The shared contact includes a silicide layer, a metal plug layer, and a conductive metal layer.

Method and structure of forming sidewall contact for stacked FET

A semiconductor device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer of the semiconductor device includes a standard-gate field-effect transistor. The second semiconductor layer of the semiconductor device includes an extended-gate field-effect transistor. The first semiconductor layer and the second semiconductor layer are formed on top of one another.

Stacked FETS including devices with thick gate oxide

A semiconductor device includes a substrate with a planar top surface. At least a first gate cut stressor within a first gate cut region separates a first transistor region from a second transistor region. The first gate cut stressor is directly upon the planar top surface and applies a first tensile force perpendicular to a channel of the first transistor region and perpendicular to a channel of the second transistor region. The tensile force may improve hole and/or electron mobility within a transistor in the first transistor region and within a transistor in the second transistor region. The gate cut stressor may include a lower material within the gate cut region and an upper material upon the lower material. Alternatively, the gate cut stressor may include a liner material that lines the gate cut region and an inner material upon the liner material.

Stressed material within gate cut region

Semiconductor devices and methods of making the same include a first lower device and a second lower device on a substrate. A first upper device is over the first lower device and a second upper device is over the second lower device. A first lower contact extends from a height above the first upper device and makes electrical contact with a top surface and a sidewall surface of the first lower device. A second lower contact extends from a height above the second upper device and makes electrical contact with a top surface and a sidewall surface of the second lower device. An insulating barrier is between the first lower contact and the second lower contact.

Stacked FET contact formation

A vertical Josephson Junction (JJ) qubit device that is fabricated from crystalline silicon material is provided. The JJ device has a substrate of epitaxial silicon, a lower superconducting electrode that is a superconducting region of the epitaxial silicon and an upper superconducting electrode of a metallic superconductor. The JJ device also has a junction layer. A section of the junction layer between the lower and upper superconducting electrodes forms a junction of the JJ device. Resonator and/or capacitor wiring of the JJ device is also fabricated using the metallic superconductor. The superconducting region is epitaxial silicon that is doped or implanted with boron or gallium. The substrate, the junction layer, and the implanted epitaxial silicon share a contiguous crystalline structure.

Vertical silicon Josephson Junction device for qubit applications

A semiconductor structure is presented including source/drain (S/D) epitaxial growth formed over a bottom dielectric isolation region, at least one first semiconductor layer disposed within the S/D epitaxial growth in a S/D region and at least one second semiconductor layer disposed partially within a gate region. The at least one second semiconductor layer extends from the gate region into a spacer region to enable a connection to the S/D epitaxial growth. The semiconductor structure further includes a first region with adjacent devices exhibiting a first Contacted gate Poly Pitch (CPP) defining a first gate-to-gate space and a second region with adjacent devices exhibiting a second CPP defining a second gate-to-gate space, where adjacent devices exhibiting the first CPP have a smaller gate-to-gate canyon than the adjacent devices exhibiting the second CPP such that the second gate-to-gate space is greater than the first gate-to-gate space.

CPP-agnostic source-drain contact formation for gate-all-around devices with dielectric isolation

A PCM cell includes a first electrode, a heater/PCM portion electrically connected to first electrode, the heater/PCM portion comprising a PCM material, a second electrode electrically connected to the PCM material, and an electrical insulator stack surrounding the projection liner. The stack includes a plurality of first layers comprised of a first material and having a plurality of first inner sides facing towards the projection liner, and a plurality of second layers alternating with the plurality of first layers, the plurality of second layers comprised of a second material that is different from the first material, and the second plurality of layers having a plurality of second inner sides facing towards the projection liner. The plurality of second inner sides that are offset from the plurality of first inner sides forming a plurality of gaps.

Phase change memory gaps

A semiconductor structure comprises a substrate defining a first axis and a second axis in orthogonal relation to the first axis, first and second nanosheet stacks disposed on the substrate, a gate structure on each of the first and second nanosheet stacks, a source/drain region adjacent each of the first and second nanosheet stacks, a wrap-around contact disposed about each source/drain region and an isolator pillar disposed between the wrap-around contacts.

Wrap-around contact for nanosheet device

A semiconductor structure may include a resistive random access memory device embedded between an upper metal interconnect and a lower metal interconnect in a backend structure of a chip. The resistive random access memory may include a bottom electrode and a top electrode separated by a dielectric film. A portion of the dielectric film directly above the bottom electrode may be doped and crystalline. The semiconductor structure may include a stud below and in electrical contact with the bottom electrode and the lower metal interconnect and a dielectric layer between the upper metal interconnect and the lower metal interconnect. The dielectric layer may separate the upper metal interconnect from the lower metal interconnect. The crystalline portion of the dielectric film may include grain boundaries that extend through an entire thickness of the dielectric film. The crystalline portion of the dielectric film may include grains.

Back end of line embedded RRAM structure with grain growth enhancement

A semiconductor structure may include a resistive random access memory device embedded between an upper metal interconnect and a lower metal interconnect in a backend structure of a chip. The resistive random access memory may include a first electrode and a second electrode separated by a dielectric film. A portion of the dielectric film directly above the first electrode may be crystalline. The semiconductor structure may include a stud below and in electrical contact with the first electrode and the lower metal interconnect and a dielectric layer between the upper metal interconnect and the lower metal interconnect. The dielectric layer may separate the upper metal interconnect from the lower metal interconnect. The crystalline portion of the dielectric film may include grain boundaries that extend through an entire thickness of the dielectric film. The crystalline portion of the dielectric film may include grains.

Back end of line embedded RRAM structure with low forming voltage

An integrated short channel omega gate FinFET and long channel FinFET semiconductor device includes a first fin and second fin on a buried oxide (BOX) layer. The BOX layer includes a fin well outside and substantially adjoining a footprint of a respective fin. A first gate dielectric layer is upon the second fin and a second gate dielectric layer is upon the first dielectric layer. The BOX layer further includes an undercut below the first fin that exposes a portion of a bottom surface of the first fin. An omega-gate is around the first fin. A tri-gate is upon the second gate dielectric layer over the second fin.

Integrated short channel omega gate FinFET and long channel FinFET

A Josephson Junction qubit device is provided. The device includes a substrate of silicon material. The device includes first and second electrodes of superconducting metal. The device may include a nanowire created by direct ion implantation on to the silicon material to connect the first and second electrodes. The device may include first and second superconducting regions created by direct ion implantation on to the silicon material, the first superconducting region connecting the first electrode and the second superconducting region connecting the second electrode, with a silicon channel formed by a gap between the first and second superconducting regions.

Josephson junction device fabricated by direct write ion implantation

An approach to provide a semiconductor structure for a phase change memory cell with a first liner material surrounding a sidewall of a hole in a dielectric material where the hole in the dielectric is on a bottom electrode in the dielectric material. The semiconductor structure includes a layer of a second liner material on the first liner material, where the second liner material has an improved contact resistance to a phase change material. The semiconductor structure includes the phase change material abutting the layer of the second liner material on the first liner material. The phase change material fills the hole in the dielectric material. The second liner material that is between the phase change material and the first liner material provides a lower contact resistivity with the phase change material in the crystalline phase than the first liner material.

Contact resistance of a metal liner in a phase change memory cell

Growing community of inventors

Tannersville, NY, United States of America

Oleg Gluschenkov