Nvidia Corporation

Olakanmi Oluwole

Vishnu Balan

Gaurawa Kumar

Ky-Anh Tran

John Wood Poulton

Sanquan Song

Carl Thomas Gray

Dai Dai

Arif Al Amin

Venkatraman Natarajan

Shashank Mahajan

A device includes a transmitter to transmit serialized data within a differential direct-current (DC) signal over a differential output line, a multiplexer circuit coupled to the transmitter, and a calibration circuit coupled between the differential output line, a multi-phase clock, and the multiplexer circuit. The multiplexer circuit is to select the serialized data from ones of multiple input lines according to a multi-phase clock and pass the selected serialized data to the transmitter. The serialized data includes a calibration bit pattern. The calibration circuit is to capture and digitize the differential DC signal into a digital stream, measure an error value from the digital stream that is associated with distortion based on the calibration bit pattern, convert the error value into a gradient value, and correct one or more phases of the multi-phase clock to compensate for the distortion based on the gradient value.

Transmitter-based, multi-phase clock distortion correction

This disclosure relates to a receiver that includes a clock and data recovery loop and a phase offset loop. The clock and data recovery loop may be controlled by a sum of gradients for a plurality of data interleaves. The phase offset loop may be controlled by an accumulated differential gradient for each of the data interleaves.

Data recovery technique for time interleaved receiver in presence of transmitter pulse width distortion

This disclosure relates to a receiver comprising a clock and data recovery loop and a phase offset loop. The clock and data recovery loop may be controlled by a sum of gradients for a plurality of data interleaves. The phase offset loop may be controlled by an accumulated differential gradient for each of the data interleaves.

Injection locked oscillation circuits are applied along clock distribution circuit paths to increase clock signal bandwidth, reduce duty cycle error, reduce quadrature phase error, reduce clock signal jitter, and reduce clock signal power consumption.

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Mountain View, CA, United States of America

Olakanmi Oluwole