Huawei Technologies Co., Limited

Infineon Technologies Ag

Ola Pettersson

Christian Grewing

Andrej Litwin

Anders Emericks

Anders Jakobsson

Bingxin Li

A method and apparatus for generating a carrier frequency signal is disclosed. The method includes generating a first frequency signal; injecting a modulation signal at a first point of the two-point modulation architecture; generating a second frequency signal from the modulation signal; introducing the second frequency signal by mixing the first frequency signal and the second frequency signal to generate a mixed frequency signal and outputting the carrier frequency signal selected from the mixed frequency signal.

Method and apparatus for generating a carrier frequency signal

A Digital Calibration System for a Phase Locked Loop includes a Tuning Voltage Controller configured to set the tuning voltage to a value; a Phase Difference Quantizer configured to output a phase difference after comparing a phase of the reference signal with a phase of the feedback signal; a Digital Controller configured to receive the phase difference of the PDQ and control a coarse tuning signal such that an average phase difference of the PDQ is 0; and a Frequency Calibration Logic configured to calibrate the feedback signal in response to the output of the DC.

System and method for calibrating output frequency in phase locked loop

A method and a device for determining closed loop bandwidth characteristic of a Phase Locked Loop (PLL) () comprising a voltage controlled oscillator (VCO) () controlled by means of a tuning voltage (V) is disclosed. An embodiment of the invention compares the VCO tuning voltage (V) to a low threshold voltage (V) and a high threshold voltage (V), creating an oscillation of the VCO tuning voltage by offsetting the divider value such that the PLL () forces the tuning voltage (V) towards the high threshold voltage (V) when the low threshold voltage (V) is reached, and offsetting the divider value such that said PLL () forces the tuning voltage (V) towards the low threshold voltage (V) when the high threshold voltage (V) is reached, measuring the period of the oscillation between the high and the low threshold voltage of the VCO tuning voltage by counting the number of cycles of a reference clock signal (clk), and comparing the number of reference clock cycles to a reference number of clock cycles to determine the relative loop bandwidth of the PLL ().

Time-domain measurement of PLL bandwidth

A device for ESD (electrostatic discharge) protection of a circuit of a semiconductor device comprises a field effect transistor based varistor with gate, source and drain regions, wherein one of the source and drain regions is connected to an input/output pad of the semiconductor device, and the other one of the source and drain regions is connected to an input/output terminal of the circuit. A biasing circuit is connected to the gate region of the varistor to create an accumulation region below the gate of the varistor at normal operating voltages of said semiconductor device. The semiconductor device is preferably an integrated device on a single substrate.

Device for ESD protection of an integrated circuit

A device for ESD protection of a high frequency circuit () of a semiconductor device comprises first () and second () p-type and first () and second () n-type JFET's, wherein the first p-type JFET () is connected with its gate to a high voltage source, its source to an input/output pad () of the semiconductor device, and its drain to the source of the first n-type JFET (), the second p-type JFET () is connected with its gate to the high voltage source, its source to the drain of the second n-type JFET (), and its drain to an input/output terminal of the circuit (), the first n-type JFET transistor () is connected with its gate to ground (GND), and its drain to the input/output terminal, and the second n-type JFET transistor () is connected with its gate to ground (GND), and its source to the input/output pad ().

To protect a high-frequency integrated circuit () against higher voltages than normal operating voltages on an input/output terminal connected to a bonding pad (), a semiconductor varistor () having low and essentially constant resistance for said normal operating voltages and higher resistance for said higher voltages is integrated between the bonding pad () and the input/output terminal together with the integrated circuit ().

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Järfälla, Sweden

Ola Pettersson