Arm Limited

Anoto Ab

C Technologies Ab

Anoto Group Ab

Ola Hugosson

Erik Persson

Petter Ericson

Dominic Hugo Symes

Andreas Björklund

Jorn Nystad

Tomas Fredrik Edsö

Christer Fåhraeus

Oskar Lars Flordal

Sean Tristram Ellis

Donald Kenneth Felton

Christer F&aring;hraeus

Jeremy Davies

Pontus Borg

A video decoder configured to decode an encoded video bitstream comprises a first parsing unit and a second parsing unit, each configured to independently parse the encoded video bitstream to derive parsing state information therefrom on which subsequent parsing of the encoded video bitstream at least partially depends and to identify macroblock information for decoding. The encoded video bitstream comprises frame header information defining a sequence of frames and each frame is composed of macroblocks represented by macroblock information. A control unit of the video encoder allocates each frame of macroblock information to one of the two parsing units to parse. The two parsing units are both configured to parse frame header information to thereby each derive parsing state information for the encoded video bitstream, and the two parsing unit are each configured to parse macroblock information allocated to them, skipping macroblock information allocated to the other parsing unit.

Parallel parsing in a video decoder

A video processing system includes a video processing unit (VPU) and one or more display processing units, all having access to external memory. Video data representing frames to be displayed is generated. The VPU generates pixel data representing the frames and stores it in memory. The display processing units then read the pixel data to display the frames. The VPU is configured to generate and store in memory pixel data representing reference frames for the sequence of video frames at the full resolution of the reference frame and also at at least one lower resolution to the full resolution.

Video processing system

A video processing system comprises a video processor and an output buffer. When a new frame is to be written to the output buffer, the video processing system determines () for at least a portion of the new frame whether the portion of the new frame has a particular property. When it is determined that that the portion of the new frame has the particular property (), when a block of data representing a particular region of the portion of the new frame is to be written to the output buffer, it is compared to at least one block of data already stored in the output buffer, and a determination is made whether or not to write the block of data to the output buffer on the basis of the comparison. When it is determined that the portion of the new frame does not have the particular property (), the portion of the new frame is written to the output buffer.

Data processing systems

A data processing system comprises a video processor (). The data processing system is configured to, when a new frame () is to be encoded by the video processor (), determine for a sub-region of a set of plural sub-regions that the new frame () is divided into, whether the sub-region has changed from a previous frame (), and to control the encoding operation for the new frame () on the basis of the determination, e.g. to avoid performing motion estimation.

A video encoder and method of video encoding are provided. At an encoding stage a selected degree of quantization is applied to the encoding of macroblocks of the input video sequence and quantized part-encoded macroblocks are generated. Quantization circuitry in the encoding stage is configured to select the selected degree of quantization for each macroblock in a current slice in dependence on a complexity estimate indicative of the expected entropy encoding complexity of a predetermined set of the quantized part-encoded macroblocks defined for that macroblock.

Rate control in video encoding

A video encoding apparatus for encoding a video stream comprises a reference frame cache for reference frame video data retrieved from a reference frame storage unit in external memory, which is derived from an individual frame of the video stream. First and second source frame storage units store first and second blocks of unencoded video data taken from first and second source frames of the video stream, respectively. First and second video encoders perform first and second encoding operations to encode the first and second blocks of unencoded video data with reference to the reference frame video data cached in the reference frame cache, respectively. The first video encoder and the second video encoder perform the first encoding operation and the second encoding operation in parallel with one another.

Video encoder

A data processing apparatus and corresponding method of data processing are provided. The data processing apparatus comprises a temporary data store configured to store data items retrieved from a memory, wherein the temporary data store selects one of its plural data storage locations in which to store a newly retrieved data item according to a predetermined circular sequence. An index data store is configured to store index items corresponding to the data items stored in the temporary data store, wherein presence of a valid index item in the index data store is indicative of a corresponding data item in the temporary data store. Invalidation control circuitry performs a rolling invalidation process with respect to the index items stored in the index data store, comprising sequentially processing the index items stored in the index data store and selectively marking the index items as invalid according to a predetermined criterion.

Invalidation of index items for a temporary data store

A data processing apparatus is provided comprising a plurality of master devices configured to issue memory access requests including virtual addresses. A memory management unit is configured to receive memory access requests and to translate a virtual address included in a memory access request from a requesting master device into a physical address indicating a storage location in memory. The memory management unit has an internal storage unit having a plurality of entries wherein indications of corresponding virtual address portions and physical address portions are stored. The memory management unit is configured to select an entry of the internal storage unit in dependence on the virtual address and an identifier of the requesting master device. Conflict between the master devices in their usage of the internal storage unit is thus avoided.

Memory management unit

A data processing apparatus is provided, comprising plural processing units configured to execute plural processes, a storage unit configured to store data required for the plural processes; and a protection unit configured to control access by the plural processes to the storage unit. The protection unit is configured to define an allocated access region of the storage unit for each process of the plural processes, wherein the protection unit is configured to deny access for each the process outside the allocated access region and wherein allocated access regions are defined to be non-overlapping. The protection unit is configured to define each allocated access region as a contiguous portion of the storage unit between a lower region limit and an upper region limit, and the protection unit is configured such that when the lower region limit is modified the lower region limit cannot be decreased and such that when the upper region limit is modified the upper region limit cannot be decreased.

Protection circuity and method for controlling access by plural processes to a memory

A data arrayto be stored is first divided into a plurality of blocks. Each blockis further sub-divided into a set of sub-blocks, and a set of data for each sub-blockis then stored in a body data buffer. A header data blockis stored for each blockat a predictable memory address within a header buffer. Each header data block contains pointer data indicating the position within the body bufferwhere the data for the sub-blocks for the blockthat that header data blockrelates to is stored, and data indicating the size of the stored data for each respective sub-block

Methods of and apparatus for storing data in memory in data processing systems

To encode and compress a data array, the data arrayis first divided into a plurality of blocks. A quadtree representation is then generated for each blockby initializing each leaf node of the quadtree to the value of the data element of the blockof the data arraythat the leaf node corresponds to, and initializing each non-leaf node to the minimum value of its child nodes, and then subtracting from each node except the root node the value of its parent node. A set of data indicating the differences between respective parent and child node values in the quadtree representing the block of the data array is then generated and stored, together with a set of data representing a quadtree indicating the number of bits that have been used to signal the respective difference values.

Methods of and apparatus for encoding and decoding data in data processing systems

A data arrayto be stored is first divided into a plurality of blocks. Each blockis further sub-divided into a set of sub-blocks, and a set of data for each sub-blockis then stored in one or more body blocks. A header data blockis stored for each blockat a predictable memory address within a header buffer. Each header data block contains pointer data indicating the position within a body blockwhere the data for the sub-blocks for the blockthat that header data blockrelates to is stored, and data indicating the size of the stored data for each respective sub-block

A data processing apparatus comprises a primary processor, a secondary processor configured to perform secure data processing operations and non-secure data processing operations and a memory configured to store secure data used by the secondary processor when performing the secure data processing operations and configured to store non-secure data used by the secondary processor when performing the non-secure data processing operations, wherein the secure data cannot be accessed by the non-secure data processing operations, wherein the secondary processor comprises a memory management unit configured to administer accesses to the memory from the secondary processor, the memory management unit configured to perform translations between virtual memory addresses used by the secondary processor and physical memory addresses used by the memory, wherein the translations are configured in dependence on a page table base address, the page table base address identifying a storage location in the memory of a set of descriptors defining the translations, wherein the page table base address is defined by the primary processor and cannot be amended by the secondary processor.

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Lund, Sweden

Ola Hugosson