Nordic Semiconductor Asa

Ola Bruset

Werner Luzi

Carsten Wulff

Ruben Undheim

Tor Oyvind Vedal

Sverre Wichlund

David Alexandre Engelien-Lopes

Phil Corbishley

Stein Erik Weberg

Harald Garvik

Tor Øyvind Vedal

Per Carsten Skoglund

Eivind Olsen

Shankkar Balasubramanian

Lukasz Farian

Bard Haaheim

Stein-Erik Weberg

Tor ØYvind Vedal

According to an aspect, there is provided a method for transmitting a low-power radio signal, comprising: transmitting, by a radio device, a data radio signal by using binary frequency-shift-keying modulation introducing a phase change between consecutive bit intervals in the data radio signal; and transmitting, by the radio device, a wake-up radio signal using the binary frequency-shift-keying modulation where repetition coding is applied before the frequency-shift-keying to eliminate the phase change between consecutive bit intervals in the wake-up radio signal.

Low-power radio transmissions

According to an aspect, there is provided an all-digital phase-locked loop, ADPLL, for a radio receiver, transmitter or transceiver. The ADPLL comprises a time-to-digital converter for generating a digital time signal based on an external reference clock signal and a feedback signal, a switched capacitor digitally controlled oscillator, SC-DCO, for generating a radio frequency signal used as the feed-back signal, a phase-locked loop for controlling the SC-DCO based on the digital time signal for achieving a phase and frequency lock and digital processing means. The digital processing means are configured to maintain, in at least one memory, a lookup table defining a plurality of switching configurations of the SC-DCO corresponding to a plurality of frequencies of the radio frequency signal and to cause the phase-locked loop controller to adjust the switching configuration of the SC-DCO according to the lookup table.

Fast-locking all-digital phase-locked loop and applications thereof

A voltage divider circuit arrangement includes a resistive divider circuit portion constructed from first and second resistors (R, R) The first and second resistors are connected in series and are arranged to provide a refresh voltage (Vrefresh) at a refresh node between them. A capacitive divider circuit portion is constructed from first and second capacitors (C, C). The first and second capacitors are connected in series and are arranged to provide an output voltage (Vout) at an output node. A switching circuit portion is arranged intermittently to switch the voltage divider circuit arrangement between a first mode wherein the resistive divider is enabled and the output node is connected to the refresh node, and a second mode wherein the resistive divider is disabled and the output node is not connected to the refresh node.

Voltage dividers

A duty cycle conversion circuit portion comprises N inverters, wherein N is an integer greater than two. The duty cycle conversion circuit is arranged to receive N input signals each having a duty cycle between 1/N and 2/N. Each of the N input signals is applied to a respective input terminal of one of the N inverters such that each inverter receives a different input signal. Each of the N input signals is applied to a respective power terminal of one of the N inverters such that each inverter is powered by a different input signal. Each inverter receives different input signal at its respective input terminal to the input signal applied to its respective power terminal.

Duty cycle converter

A method of demodulating an amplitude modulated radio signal is disclosed. The method comprises directing the modulated signalto both a phase detectorand an edge detector, and using the respective output signalsof the phase detectorand edge detectorto determine an end of a modulation symbolin the signal

AM demodulation with phase and symbol edge detection

A radio transmitter () comprises an encoder () that receives one or more variable message bits, and encodes each message bit that has a first value as a predetermined first binary chip sequence and encodes each message bit that has the opposite value as a predetermined second binary chip sequence. The radio transmitter () transmits data packets, each comprising (i) a predetermined synchronization portion, comprising one or more instances of the first binary chip sequence, and (ii) a variable data portion, comprising one or more encoded message bits output by the encoder. A radio receiver () receives such data packets. It uses the synchronization portion of a received data packet to perform a frequency and/or timing synchronization operation, and then decodes message bits from the data portion of the data packet.

Radio communication

A phase locked loop frequency synthesizer is arranged to provide a target frequency output signal for a radio transmitter or receiver. The synthesizer comprises: a voltage controlled oscillator () operating at a first frequency; a first, fixed frequency divider to provide a second frequency, a pre-scaler to provide a variable frequency division of said second frequency to produce a third frequency, said pre-scaler comprising: a second frequency divider () connected to said first output () and providing a second output at a second frequency; and a phase detector () controlling said voltage controlled oscillator () on the basis of a comparison between a reference signal and a signal dependent on said third frequency; wherein the synthesizer is configured so that said first output () provides said target frequency output signal.

Frequency synthesizer

An integrated oscillator circuit comprises an oscillator configured to be switched between a first frequency and a second frequency. A switching circuit receives an input representing a target frequency and switches the oscillator between the first and second frequencies at intervals determined by the input, so as to cause the average output frequency of the oscillator to approximate the target frequency.

Low-power oscillator

A temperature sensing device for an integrated circuit comprises an oscillator () having a characteristic frequency dependent on the temperature and a digital counter () arranged to count a number of pulses generated by the oscillator () in a given time interval, or the time taken for the oscillator to generate a given number of pulses. Either of these gives a measured value. The device is configured to use a difference between the measured value and a stored reference value in a linearisation algorithm to estimate a temperature.

Semiconductor temperature sensors

An integrated-circuit, continuous-time, sigma-delta analog-to-digital converter has a single-ended analog input, a converter reference input, and a ground connection. The converter has a resistor-capacitor integrator arranged to receive the single-ended analog input. The integrator comprises a differential amplifier. The converter also has a clocked comparator connected to an output from the integrator, and circuitry arranged so that reference inputs to the amplifier and to the comparator can be maintained at a common voltage derived from the converter reference input.

Analogue-to-digital converter

An integrated-circuit, continuous-time, sigma-delta analogue-to-digital converter has a single-ended analogue input, a converter reference input, and a ground connection. The converter has a resistor-capacitor integrator arranged to receive the single-ended analogue input. The integrator comprises a differential amplifier. The converter also has a clocked comparator connected to an output from the integrator, and circuitry arranged so that reference inputs to the amplifier and to the comparator can be maintained at a common voltage derived from the converter reference input.

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Trondheim, Norway

Ola Bruset