Canon Kabushiki Kaisha

Oki Minabe

Shinji Shiraga

Masayuki Odagawa

Transaction-level simulation in which communication over a bus is performed by using a transaction. The transaction includes information indicating whether information is attribute information that is mapped to hardware and includes attribute information that is not mapped to hardware. The transaction is received, time information which is attribute that is not mapped to hardware is read from the transaction, and the result of the simulation based on the read time information is outputted.

Simulation apparatus and method

A power saving type information processing apparatus is provided which is not expensive and can provide a high interruption performance without using an expensive and dedicated memory and a complicated software process. After an SDRAM setting register of an SDRAM controller outputs a SELF allowance signal for allowing SDRAM to transfer to a power saving mode from a normal operation mode, a WAITI command fetch detecting circuit outputs a WAITI command detecting signal. In this case, SDRAM is made to transfer to the power saving mode. If a CPU detects an external interruption while SDRAM is in the power saving mode, SDRAM is returned to the normal operation mode irrespective of settings of the SDRAM setting register.

Growing community of inventors

Kita-ku, Japan

Oki Minabe