Advanced Micro Devices Corporation

Oikwan Tsang

Yatin Acharya

Hung Duy Vo

Yi Cheng

Dennis Tunglin Lee

Colin D Nayler

Boon-Aik Ang

Prasant Kumar Vallur

Ramon Mangaser

Srikanth Reddy Gruddanti

Krishna Reddy Mudimela Venkata

Dennis Lau

Mark William Knecht

Zhen-Hua Liu

Phil Keller

Kalaine Mak Wong

A clock circuit for clock gating using a cascaded clock gating control signal, including: a first B-latch accepting, as input, a clock gating control signal and enabled by a first clock signal; a second B-latch accepting, as input, an output from the first B-latch and enabled by a second clock signal; and a first logic outputting, based on the first B-latch, a first gated clock signal; and a second logic outputting, based on the second B-latch, a second gated clock signal.

Clock gating using a cascaded clock gating control signal

A network node has multiple physical layer devices (PHYs), multiple media access controllers (MACs), and means for gathering information regarding the capabilities of other nodes on the network. The node capability information may be gathered using hardware or software, and may involve gathering information from data frames received by the node, and/or from capability and status announcement frames received by the node. The node capability information gathered and the node topology determined may be utilized in selecting one of the MACs as an active MAC for monitoring a network medium, and/or in selecting one of the PHYs as an active PHY for transmission of frames onto the network medium. The PHYs of the interface in an exemplary embodiment are able to transmit and receive data frames or packets which are in accordance with different home phoneline networking alliance (HPNA) specifications, for example, HPNA 1.0 and HPNA 2.0.

Method to select dynamically between MACs of network device depending on network topology

The network interface device has multiple blocks having internal connections, and has an external interface. The network interface device is configurable to reroute one or more of the internal connections onto the external interface to allow testing of the blocks of the device. The external interface may also be coupled so as to pass data between the network interface device and higher levels in a network protocol stack. In an exemplary embodiment a network interface device has a media access controller (MAC) and a physical layer device (PHY). An internal media independent interface (MII) between the MAC and the PHY may be selectively rerouted to an external MII for independently testing operation of either the MAC or the PHY.

Programmable bi-directional MII testing methodology and device including same

A physical layer transceiver of a home network station connected to a telephone medium has an architecture enabling adaptation of detection circuitry based on received network signals to enable reliable recovery of data signals. The physical layer transceiver includes an input amplifier that amplifies network signals according to one of 128 gain settings set by a receiver gain control signal. A signal conditioning circuit includes an envelope detector configured for outputting an envelope of the amplified received signal, and an energy detector configured for outputting an energy signal of the amplified received signals. The envelope signal and the energy signal are supplied to slicer threshold circuits, configured for outputting noise, peak, data event and energy event signals based on noise threshold, peak threshold, data transition threshold, and energy threshold signals, respectively. A digital controller controls the input amplifier gain and the threshold values, and adjusts the gain and threshold values based on the noise event signal and the peak event signal within an access ID (AID) interval. Hence, the receiver can be optimized on a per-packet basis for receiving network signals by adjusting the receiver portion during the AID preamble phase of the data packet. Gain control may also be used by the digital controller on the transmitter portion to selectively adjust the output gain for optimizing transmission to a destination home network station.

Physical layer transceiver architecture for a home network station connected to a telephone line medium

An input buffer for an integrated circuit and providing reduced sensitivity to input noise present in a transmission line environment. This input buffer deskews an input signal where the rise time is much slower than the fall time, such as that from an open-collector output driver, so that the rising edge propagation delay and falling edge propagation delay of the input buffer are approximately equal.

Transmission-line-noise immune input buffer

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San Jose, CA, United States of America

Oikwan Tsang