Sandisk Technologies Inc.

Ohwon Kwon

Kou Tei

Xiang Yang

Chia-Kai Chou

Jongyeon Kim

Jiahui Yuan

Tai-Yuan Tseng

Iris Lu

Arka Ganguly

Yonggang Wu

Yan Li

Deepanshu Dutta

James K Kai

Man Lung Mui

Yu-Chung Lien

Hao Nguyen

Guirong Liang

Yuki Mizutani

Hiroki Yabe

Qui V Nguyen

Yanjie Wang

Abu Naser Zainuddin

Kenneth Louie

Jong Hak Yuh

Anirudh Amarnath

Amul Dhirajbhai Desai

Feng Lu

Yuedan Li

Vsnk Chaitanya G

Sirisha Bhamidipati

Yasue Yamamoto

Techniques are presented to reduce sense amplifier noise from parasitic capacitances that can affect the internal transfer of a data value from a data latch to a sensing node. To transfer the data value, the sensing node is pre-charged and the data value used to set the control gate voltage on a transistor in a discharge path for the sensing node. In the discharge path, the transistor is connected in series with a switch, so that when the switch is turned on, the data value on the transistor's control gate will determine whether or not the sensing node discharges. To reduce noise in the process, before the data value is used to bias the discharge path transistor's control gate, a node between the transistor and switch is charged. Additionally, a lower voltage level can be used to turn on the discharge path switch.

Noise reduction in sense amplifiers for non-volatile memory

The memory device includes a chip with circuitry, a plurality of memory blocks, and a plurality of bit lines. The memory blocks include an array of memory cells, and the circuitry either overlies or underlies the array of memory cells. The bit lines are divided into two portions that are electrically connected with one another via at least one transistor so that at least one portion of each bit line can be charged independently of the other portion of the same bit line.

Low power read method and a memory device capable thereof

A memory system having a dynamic supply voltage to sense amplifiers. The supply voltage has a higher magnitude when charging inhibited bit lines during a program operation and a lower magnitude when verifying/sensing memory cells. Reducing the magnitude of the supply voltage saves power and/or current. However, if the lower magnitude were used when the inhibited bit lines are charged during the program operations, some of the memory cells that should be inhibited from programming might experience at least some programming. Using the higher magnitude supply voltage during bit line charging of the program operation assures that the inhibited bit lines are charged to a sufficient voltage to keep drain side select gates of NAND strings off so that the NAND channel will boost properly to inhibit programming of such memory cells.

Dynamic sense amplifier supply voltage for power and die size reduction

An apparatus includes a control circuit and a plurality of non-volatile memory cells arranged in a plane of a memory die. The plane includes a first word line including a first word line portion coupled to a corresponding first group of the non-volatile memory cells, and a second word line including a second word line portion coupled to a corresponding second group of the non-volatile memory cells, the second word line different from the first word line. The control circuit is configured to apply a first voltage to the first word line portion and apply a second voltage to the second word line portion to concurrently read the first group of the non-volatile memory cells and the second group of the non-volatile memory cells. The first group of the non-volatile memory cells and the second group of the non-volatile memory cells each store less than a page of data.

Pseudo multi-plane read methods and apparatus for non-volatile memory devices

A memory apparatus and method of operation are provided. The memory apparatus includes memory cells connected to word lines and disposed in memory holes organized in rows grouped in strings. The memory cells are configured to retain a threshold voltage. The rows include full circle rows and semi-circle rows in which the memory holes are partially cut by a slit half etch. The memory holes of the semi-circle rows are coupled semi-circle bit lines and the memory holes of the full circle rows are coupled to full circle bit lines. A control means is configured to erase the memory cells in an erase operation. During the erase operation, the control means creates a capacitive coupling between each of the semi-circle bit lines and at least one neighboring one of the full circle bit lines to increase a semi-circle erase voltage applied to each of the semi-circle bit lines.

Neighbor bit line coupling enhanced gate-induced drain leakage erase for memory apparatus with on-pitch semi-circle drain side select gate technology

A control circuit connected to non-volatile memory cells applies a programming signal to a plurality of the non-volatile memory cells in order to program the plurality of the non-volatile memory cells to a set of data states. The control circuit performs program verification for the non-volatile memory cells, including applying bit line voltages during program verification based on word line position and data state being verified.

Non-volatile memory with adjusted bit line voltage during verify

Technology for mitigating interference to select transistors in 3D memory is disclosed. In one aspect, a control circuit pre-charges a first set of bit lines to a first voltage and pre-charges a second set of bit lines to a second voltage greater than the first voltage. The control circuit may increase the voltage on the first set of bit lines to the second voltage while the second set of bit lines are floating to couple up the voltages on the second set of bit lines to a voltage greater than the second voltage. The higher voltage on the second set of bit lines compensates for interference that some of the select transistors may experience from an adjacent select line. For example, the higher voltage can prevent a leakage current in the select transistors from occurring. Preventing the leakage current can improve boosting of NAND channel voltages, thereby preventing program disturb.

Mitigating neighbor interference to select gates in 3D memory

Technology is disclosed herein for testing circuitry that controls memory operations in a memory structure having non-volatile memory cells. The testing of the circuitry can be performed without the memory structure. The memory structure may reside on one semiconductor die, with sense blocks and a control circuit on another semiconductor die. The control circuit is able to perform die level control of memory operations in the memory structure. The control circuit may control the sense blocks to simulate sensing of non-volatile memory cells in the memory structure even though the sense blocks are not connected to the memory structure. The control circuit verifies correct operation of the semiconductor die based on the simulated sensing. For example, the control circuit may verify correct operation of a state machine that controls sense operations at a die level. Thus, the operation of the semiconductor die may be tested without the memory structure.

Simulating memory cell sensing for testing sensing circuitry

A data storage includes a memory array including a plurality of memory cells, and peripheral circuitry disposed underneath the memory array. The peripheral circuitry includes an M-tier sense amplifier (SA) circuit including X stacks of SA latches, wherein each SA latch is respectively coupled to a bit line of a memory cell of the plurality of memory cells; and an N-tier memory cache data (XDL) circuit including Y stacks of XDL latches, wherein M is less than N, and X is greater than Y. The peripheral circuitry further includes data path circuitry coupling (i) each SA latch of the X stacks of SA latches to (ii) a respective XDL latch of the Y stacks of XDL latches.

Sense amplifier mapping and control scheme for non-volatile memory

A data storage system includes a storage medium coupled to a storage controller via an electrical interface connected to a plurality of input/output (IO) pads of the storage medium. The storage medium receives a read or write instruction from the storage controller via the IO pads, associates the read or write instruction with memory cells of a first block of a first plane of a plurality of planes of the storage medium, and adjusts a word line voltage level or a source line voltage level for the first block of the first plane based on (i) a position of the first plane with respect to the IO pads of the storage medium and (ii) a position of the first block within the first plane.

Block-dependent cell source bounce impact reduction in non-volatile memory

A storage device is disclosed herein. The storage device, comprises: a non-volatile memory including control circuitry and an array of memory cells formed using a set of word lines and a set of bit lines; and a reference current generator circuit configured to receive an input voltage from a voltage supply and generate therefrom a plurality of outputs, each output of the plurality of outputs used to generate one or more bias voltages/currents for one or more control signals. The control circuitry is configured to: receive a refresh read operation command; and adapt operation of the reference current generator circuit based on receiving the refresh read operation command. This proposal is also applicable for other test modes, such as SA stress, soft and preprogram, and SA test modes.

Reference current generator control scheme for sense amplifier in NAND design

Apparatuses and techniques are described for reducing read time in a memory device. A source voltage signal, Vcelsrc, and a body voltage signal, Vp-well, of a source region and a p-well, respectively, of a substrate of a NAND string are controlled to reduce the channel resistance. Vcelsrc can be temporarily reduced, e.g., provided with a negative voltage kick, while Vp-well is non-decreasing during a read operation. The negative voltage kick decreases a body bias of the NAND string in its channel to reduce the channel resistance and increase the current. The negative voltage kick can be initiated when a bit line clamp transistor is made conductive to allow a current to flow in the NAND string. The magnitude and duration of the negative voltage kick can be adjusted based on various factors.

Memory device with temporary kickdown of source voltage before sensing

An example of an apparatus includes a plurality of memory cells arranged in a plurality of NAND strings that are connected to a source line and a control circuit connected to the source line. The control circuit is configured to provide a first current to the source line to pre-charge the source line to a target voltage for sensing data states of the plurality of memory cells and provide a second current to the source line to return the source line to the target voltage in a recovery period between sensing data states. The control circuit is configured to provide the second current at any one of a plurality of current levels.

Source line voltage control for NAND memory

An apparatus and method for a multi-state verify of a memory array are provided. A sense circuit of a memory device is connected to a bit line of the memory array. The sense circuit includes a first voltage clamp, a second voltage clamp, and a program data latch disposed on the bit line. The first and second voltage clamps are biased to first and second voltages, respectively, where the first voltage is lower than the second voltage. When a high bias is applied to the program data latch, the program data latch is in an OFF state, and the first voltage clamp limits the bias on the bit line to the first voltage. When a low bias is applied to the program data latch, the program data latch is in an ON state, and the second voltage clamp limits the bias on the bit line to the second voltage.

Multi BLCS for multi-state verify and multi-level QPW

A memory device is provided including physical block circuitry including a first lateral network arrangement and a second lateral network arrangement. Each of the first and second lateral network arrangements includes a single generator configured to output both a sense amplifier voltage VHSA and a data latch voltage VDDSA, in each of a first mode and a second mode. In the first mode, during which read and program verify and other operations may occur, the generator receives VHSA as a feedback signal and in the second mode, during which programming, POR, and EVFY operations may occur, the generator receives VDDSA as a feedback signal.

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Pleasanton, CA, United States of America

Ohwon Kwon