Mellanox Technologies, Ltd.

Beamr Imaging Ltd.

Ohad Markus

Dotan David Levi

Assaf Weissman

Eyal Frishman

Shie Mannor

Dror Porat

Aviad Raveh

Gal Chechik

Assaf Hallak

Eshed Ram

Uri Gadot

Tamar Shoham

Dror Gill

Tal Anker

Alexander Zheludkov

Pavel Titkov

Nikolay Terterov

Alexey Mitkovets

Alexey Martemyanov

In one embodiment, a system includes a hardware accelerator to receive video data of multiple video frames, divide each of the video frames into respective blocks, compute encoding assist data including at least one video encoding parameter type for each of the respective blocks of each of the video frames, and store respective portions of the encoding assist data across respective database tables, and an interface to provide the respective database tables to video encoding software running on a processor.

Hardware accelerated video encoding

A system includes a processing device to receive video content, metadata related to the video content, and a target bit rate for encoding the video content. The processing device further detects a content type of the video content based on the metadata and encodes hardware to perform frame encoding on the video content. The system further includes a controller coupled between the processing device and the encoding hardware. The controller is programmed with machine instructions to generate first QP values on a per-frame basis using a frame machine learning model with a first plurality of weights. The first plurality of weights depends at least in part on the content type and the target bit rate. The controller further provides the first QP values to the encoding hardware for rate control of the frame encoding.

Content-aware, machine-learning-based rate control

A system includes a processing device to receive a video content, a quality metric, and a target bit rate for encoding the video content. The system includes encoding hardware to perform frame encoding on the video content and a controller coupled between the processing device and the encoding hardware. The controller is programmed with machine instructions to generate first QP values on a per-frame basis using a frame machine learning model with a first plurality of weights. The first plurality of weights depends at least in part on the quality metric and the target bit rate. The controller is further programmed to provide the first QP values to the encoding hardware for rate control of the frame encoding.

Quality-metric-agnostic rate control

A video coding system including an acceleration device including input circuitry configured, for each of a first plurality of video frames to be encoded, to receive an input including at least one raw video frame and at least one reference frame, and to divide each of the first plurality of video frames to be encoded into a second plurality of blocks, and similarity computation circuitry configured, for each one of the first plurality of video frame to be encoded: for each the block of the second plurality of blocks, to produce an intra-prediction hint and an intra-prediction direction. Related apparatus and methods are also provided.

Video coding system

A video processor includes a memory and a processor. The processor is coupled to memory and is configured to store in the memory (i) multiple raw frames belonging to a Group of Pictures (GOP) to be processed, and (ii) one or more reference frames. The processor is further configured to select for multiple target blocks having a same block-location in respective raw frames associated with a common reference frame, a common search region in the common reference frame, and before selecting another search region, to apply at least two motion estimation operations using at least two of the target blocks and the common search region, to estimate respective at least two Motion Vectors (MVs).

Efficient video motion estimation by reusing a reference search region

Described embodiments include a system that includes one or more buffers and circuitry. The circuitry is configured to process a plurality of input values, by identifying each of the input values that is not zero-valued, and, for each value of the identified input values, computing respective products of coefficients of a kernel with the value and storing at least some of the respective products in the buffers. The circuitry is further configured to compute a plurality of output values, by retrieving respective sets of stored values from the buffers, at least some of the retrieved sets including one or more of the products, and summing the retrieved sets. The circuitry is further configured to output the computed output values. Other embodiments are also described.

Accelerated convolution in convolutional neural networks

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Haifa, Israel

Ohad Markus