Intel Corporation

National Semiconductor Corporation

Winbond Electronics Corporation

Lenovo (singapore) Pte. Ltd.

Dsp Group Limited

Cct Creative Construction Tools Ltd.

Nation Semiconductor Corporation

Ohad Falik

Eliezer Weissmann

Sridhar Muthrasanallur

Ilan Pardo

Debendra Das Sharma

David J Harriman

Robert G Blankenship

Mahesh U Wagh

Mark B Rosenbluth

Jasmin Ajanovic

Scott Dion Rodgers

Anil Vasudevan

Prashant Sethi

Ajay V Bhatt

James E Akiyama

Eran Tamari

Doron Shamia

Peter J Barry

Abraham Mendelson

Ben-Zion Friedman

James B Crossland

Victor Adrian Flachs

Avi Mendelson

Gideon Intrater

Gilbert A Neiger

Alon Naveh

Gideon Gerzon

Rajesh Sankaran Madukkarumukumana

Ryan Donovan Wells

Michael Mishaeli

Michael E Deisher

Jacob Doweck

Jose P Allarey

Douglas Raymond Moran

Jawad Haj-Yihia

Michal Schramm

Yehezkel Friedman

Gadi Erlich

Tsung-Yuan Charles Tai

Ren Wang

Christian Maciocco

Nadav Shulman

Ron Gabor

Lihu Rappoport

Shaun M Conrad

Kevin B Stanton

William Knolla

Jack Doweck

Ilia Stolov

Anthony S Bock

Yulia Kurolap

Avi (Abraham) Mendelson

Aharon Ostrer

Yair Baydatch

Sm M Rahman

Randall Scott Springfield

Efraim Rotem

Paul S Diefenbaugh

Michael E Kounavis

Alexander Gendler

Mikal Hunsaker

Eliezer Tamir

Devadatta V Bodas

Nir Rosenzweig

Robert E Gough

Joseph Wayne Freeman

James Stephen Rutledge

Robert W Strong

Gokcen Cilingir

Eliel Louzoun

Yuval Itkin

Anil Aggarwal

Nimrod Diamant

Justin J Song

Michael Behar

Israel Diamand

Valery Teper

Ilan Margalit

Roni Rosner

Zeev Collin

Chaim Bendelac

Zigi Walter

Itay Franko

Isaac Karpel

Christopher Hall

Hai Ming Khor

Paul Joseph Kramer

Jered Michael Sandner

Leonid Azriel

Alberto Sandbank

Jonathan Levy

Oz Shitrit

Jenny Chang

Dan Biran

Pierre-Louis Bossart

Peter A Dice

Erik C Bjorge

Ravi Venkatesan

Shlomi Shua

Henrietta Bezbroz

Methods and apparatus to implement multiple inference compute engines are disclosed herein. A disclosed example apparatus includes a first inference compute engine, a second inference compute engine, and an accelerator on coherent fabric to couple the first inference compute engine and the second inference compute engine to a converged coherency fabric of a system-on-chip, the accelerator on coherent fabric to arbitrate requests from the first inference compute engine and the second inference compute engine to utilize a single in-die interconnect port.

Methods and apparatus to implement multiple inference compute engines

Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.

Linear to physical address translation with support for page attributes

Systems, apparatus and methods are described including operations for a flexible neural network accelerator.

Flexible neural network accelerator and methods therefor

Techniques to output a media stream, capture a media stream, or synchronize the output or capture of the media stream at a specified time are described. A media stream output or capture apparatus may include a media processor to receive a media stream to output or a request to capture a media stream and a start time. A buffer generator may be included to generate an input or an output buffer and a media mixer may be included to mix the media stream into the output buffer at the start time or capture the media stream from the input buffer at the start time.

Hardware assisted media playback and capture synchronization

Systems, apparatus and methods are described including operations for a dual mode GMM (Gaussian Mixture Model) scoring accelerator for both speech and video data.

Speech and video dual mode gaussian mixture model scoring accelerator

A device for positioning a tile, comprising: a beam reader for receiving a laser beam within a predetermined range of locations, and providing a height indication; a level for providing a tilt indication of a tilt of the device; a processor for receiving the height and tilt indications, and combining them for determining gradient and height of a part of the tile; a display component for displaying in at least two dimensions positioning information for the device, the positioning information relating to the gradient and height of the tile part, as obtained by combining the height and tilt indications, wherein the beam being received at a predetermined location within the range of locations, and the level indicating that the device is at a predetermined tilt, provides that the tile being positioned is at a required height, and wherein the device is adapted to be stably placed on the tile.

Method and apparatus for assisting in tiling

Examples are disclosed for exchanging a key between an input/output device for network device and a first processing element operating on the network device. Data having a destination associated with the first processing element may be received by the input/output device. The exchanged key may be used to encrypt the received data. The encrypted data may then be sent to a buffer maintained at least in part in a memory for the network device. The memory may be arranged to enable sharing of the buffer with at least a second processing element operating on the network device. Examples are also disclosed for the processing element to receive an indication of the storing of the encrypted data in the buffer. The processing element may then obtain the encrypted data from the buffer and decrypt the data using the exchanged key.

Shared buffers for processing elements on a network device

Embodiments of an apparatus for improving performance for events handling are presented. In one embodiment, the apparatus includes a number of processing elements and task routing logic. If at least one of the processing elements is in a turbo mode, the task routing logic selects a processing element for executing a task based at least on a comparison of performance losses.

Methods and apparatus to improve turbo performance for events handling

Embodiments of systems, apparatuses, and methods for posting interrupts to virtual processors are disclosed. In one embodiment, an apparatus includes look-up logic and posting logic. The look-up logic is to look-up an entry associated with an interrupt request to a virtual processor in a data structure. The posting logic is to post the interrupt request in a data structure specified by information in the first data structure.

Posting interrupts to virtual processors

A processor includes at least one core, a power control unit, and a first interconnect to couple with a peripheral controller. The first interconnect is to provide a first uni-directional communication path for communication of first power management data from the processor to the peripheral controller. Other embodiments are described and claimed.

Interconnect to communicate information uni-directionally

Systems, apparatus and methods are described including operations for memory access via direct memory access engines, of a Gaussian Mixture Model Accelerator, corresponding to individual data streams.

Gaussian mixture model accelerator with direct memory access engines corresponding to individual data streams

Methods and apparatus relating to controlling power consumption by a power management link are described. In one embodiment, the physical interface of a power management (PM) link is shut down when a processor is in a sleep state (e.g., to conserve power), while maintaining the availability of the processor for communication to a (e.g., embedded) controller over the PM link. Other embodiments are also disclosed and claimed.

Controlling power consumption by power management link

Methods and apparatus relating to measuring time offsets between devices with independent silicon clocks are described. In some embodiments, logic is provided to synchronize a first clock of a first agent with a second clock of a second agent based on one or more messages exchanged between the first agent and the second agent and a platform time. The first agent and the second agent are coupled via a link. Other embodiments are also disclosed and claimed.

Measuring time offsets between devices with independent silicon clocks

A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Atomic operations in PCI express

Growing community of inventors

Kfar Saba, Israel

Ohad Falik