Samsung Electronics Co., Ltd.

Oh-Suk Kwon

June Hyung Lee

Heung-Soo Im

Ji-sang Lee

Ki-Hwan Choi

Sung-won Yun

In-Young Kim

Ji-Sang Lee

Hyoung-Woo Lee

A nonvolatile memory device, including a first latch unit and a nonvolatile memory cell, and a method of writing data in a nonvolatile memory device are provided. The method includes receiving a first writing command or a second writing command from outside of the nonvolatile memory device, and writing first data stored in the first latch unit in the nonvolatile memory cell in response to the first or second writing command. The first data is retained in the first latch unit until the writing of the first data stored in the first latch unit in the nonvolatile memory cell is completed.

Nonvolatile memory device and method of writing data in nonvolatile memory device

A program verification circuit comprises a failed state counting unit and a failed bit counting unit. The failed state counting unit counts failed program states among a plurality of program states, and generates a first program mode signal indicating whether counting of failed bits is required. The failed bit counting unit selectively counts failed bits in response to the first program mode signal, and generates a second program mode signal indicating whether a program operation is completed.

Nonvolatile memory device and related program verification circuit

A page buffer includes a sense latch, a data latch and a page buffer controller. The sense latch is connected to a bit line, and is configured to set stored data in response to a sense latch control signal, and to change the stored data in response to a signal applied to the bit line in a data verification operation. The data latch is configured to store multi-bit data to be programmed in a program operation, and to set stored data in response to a data latch control signal in the data verification operation. The page buffer controller is configured to control the bit line in accordance with the multi-bit data stored in the data latch in the program operation, and to output the sense latch control signal and the data latch control signal in accordance with the multi-bit data stored in the data latch in response to a control signal in the data verification operation.

Page buffer, nonvolatile semiconductor memory device having the same, and program and data verification method

A nonvolatile memory device and programming method and apparatus therefore are described that include operatively coupled first and second sense amplifiers having first and second data registers or latches, a storage circuit for storing a data of the second amplifier, a pass/fail check circuit for checking the content of the second data register whether a cell of the memory device has been sufficiently programmed and a restore circuit for resetting the second data register for reprogramming the device until sufficiently programmed.

Memory devices with page buffer having dual registers and method of using the same

A flash memory device may include: a plurality of main bit lines; a plurality of redundant bit lines; a plurality of first page buffers respectively organized as a plurality of first page buffer groups which are connected to main bit lines; a plurality of second page buffers respectively organized as a plurality of second page buffer groups which are connected to the redundant bit lines; each of the first and second page buffers including an output P/F terminal to provide pass/fail data; a plurality of fuses corresponding to the pluralities of the first and second page buffer groups, respectively, each of the fuses having one end commonly connected to the P/F terminals in a corresponding page buffer group and the other end connected to a signal line; and a pass/fail check circuit to determine an overall pass/fail signal based upon a signal on the signal line.

Semiconductor memory device having flexible column redundancy scheme

The present invention relates to a nonvolatile semiconductor memory, that is, a flash memory and especially to a NAND type flash memory device capable of selectively controlling data input/output units by an address control. In the NAND type flash memory device, a memory cell array is divided into a plurality of blocks, and a data input/output path is selectively controlled by a predetermined data rate option and introduced addresses to perform data input/output operations at a &#xd7;8 or &#xd7;16 speed in one chip.

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Taegu Kwang Yuk, South Korea

Oh-Suk Kwon