Samsung Electronics Co., Ltd.

Oh-sang Kwon

Jung-Hoon Kim

Hyun-cheol Park

Jae-woo Kim

Sung-hyun Hwang

Chang-hyun Yim

Eui-jin Kwon

A system-on-a-chip (SOC) includes a memory system, a data processor and a read only memory (ROM). The memory system includes random access memory and a memory controller. The data processor includes at least one functional block that communicates data with the memory system via the memory controller. The ROM stores data and one or more parity bits for detecting and correcting errors in the data. The data includes chip information and/or security information for the SOC. A method of using the SOC includes storing data in the ROM that includes chip information and/or security information for the SOC; storing in the ROM the one or more parity bits for the data; reading the data and the one or more parity bits from the ROM; detecting and correcting errors in the data using the one or more parity bits; and outputting the corrected data.

System-on-a-chip storing chip data and/or security data and method of processing chip data and/or security data for a device

A receiver performing a stable operation in a burst mode is provided. The receiver transmits packet data using a preamble, and has good acquisition performance so that a synchronization part converges on a preamble interval. For the acquisition performance, the receiver senses the carrier of a received signal, detects a rough location of a burst, and in response to the result of carrier sensing, performs coarse gain control, symbol timing compensation, and frame synchronization. Then, if the frame synchronization is completed, in response to the result of frame synchronization, the receiver performs fine gain control, equalization of the signal, and carrier recovery.

Burst mode receiver and method for stable reception of packet data on telephone line

A channel equalizing and carrier recovery system for home phoneline networking alliance (HomePNA) receiver and method thereof are provided. The channel equalizing system includes a frequency diverse quadrature amplitude modulation (FD-QAM) equalizer and a quadrature amplitude modulation (QAM) equalizer. The FD-QAM equalizer receives an FD-QAM signal, determines FD-QAM tap coefficients, and equalizes the FD-QAM signal using the FD-QAM tap coefficients. The QAM equalizer receives a QAM signal, determines QAM tap coefficients, and equalizes the QAM signal using the QAM tap coefficients. The QAM equalizer receives the FD-QAM signal and determines the QAM tap coefficients during a predetermined header period. The carrier recovery circuit includes a phase detector, a loop filter, and a numerically controlled oscillator (NCO). The phase detector uses a phase difference between a reception symbol and a decision signal of the reception symbol as an instantaneous phase difference when the reception symbol is a data symbol of an FD-QAM signal or a symbol of a QAM signal, uses '0' as the instantaneous phase difference when the reception symbol is a zero symbol of the FD-QAM signal, averages instantaneous phase differences during a predetermined period or time, and outputs the result of averaging. The loop filter filters the output signal of the phase detector. The NCO generates an oscillation signal having a variable phase in response to an output signal of the loop filter so that a phase error of a reception signal can be controlled.

Channel equalizing and carrier recovery system for home phoneline networking alliance receiver and method thereof

A digital echo cancellation device is provided. The digital echo cancellation device used for a high speed bidirectional communication system includes an adaptive beamformer in the form of a plurality of finite impulse response (FIR) filters for estimating an input receiving signal, the adaptive beamformer for estimating a front part, which rapidly changes in an echo path impulse response, by adaptively estimating the input receiving signal and an orthogonalized infinite impulse response (IIR) filter for receiving the estimated signal output from the adaptive beamformer and estimating a hind part of the echo path impulse response on the basis of an IIR. According to the digital echo cancellation device, the amount of calculation and the amount of required memory is significantly reduced, convergence speed is high, and the stability of the output of the filter is improved since the impulse response of the echo path is estimated by only several tens of taps.

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Suwon, South Korea

Oh-sang Kwon